board/compulab/cm_fx6/cm_fx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for Compulab CM-FX6 board
   4  *
   5  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   6  *
   7  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   8  */
   9
  10 #include <common.h>
  11 #include <ahci.h>
  12 #include <dm.h>
  13 #include <dwc_ahsata.h>
  14 #include <env.h>
  15 #include <fsl_esdhc_imx.h>
  16 #include <init.h>
  17 #include <miiphy.h>
  18 #include <mtd_node.h>
  19 #include <netdev.h>
  20 #include <errno.h>
  21 #include <usb.h>
  22 #include <fdt_support.h>
  23 #include <sata.h>
  24 #include <splash.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <asm/arch/sys_proto.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/arch/mxc_hdmi.h>
  29 #include <asm/mach-imx/mxc_i2c.h>
  30 #include <asm/mach-imx/sata.h>
  31 #include <asm/mach-imx/video.h>
  32 #include <asm/io.h>
  33 #include <asm/gpio.h>
  34 #include <dm/platform_data/serial_mxc.h>
  35 #include <dm/device-internal.h>
  36 #include <jffs2/load_kernel.h>
  37 #include "common.h"
  38 #include "../common/eeprom.h"
  39 #include "../common/common.h"
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #ifdef CONFIG_SPLASH_SCREEN
  44 static struct splash_location cm_fx6_splash_locations[] = {
  45         {
  46                 .name = "sf",
  47                 .storage = SPLASH_STORAGE_SF,
  48                 .flags = SPLASH_STORAGE_RAW,
  49                 .offset = 0x100000,
  50         },
  51         {
  52                 .name = "mmc_fs",
  53                 .storage = SPLASH_STORAGE_MMC,
  54                 .flags = SPLASH_STORAGE_FS,
  55                 .devpart = "2:1",
  56         },
  57         {
  58                 .name = "usb_fs",
  59                 .storage = SPLASH_STORAGE_USB,
  60                 .flags = SPLASH_STORAGE_FS,
  61                 .devpart = "0:1",
  62         },
  63         {
  64                 .name = "sata_fs",
  65                 .storage = SPLASH_STORAGE_SATA,
  66                 .flags = SPLASH_STORAGE_FS,
  67                 .devpart = "0:1",
  68         },
  69 };
  70
  71 int splash_screen_prepare(void)
  72 {
  73         return splash_source_load(cm_fx6_splash_locations,
  74                                   ARRAY_SIZE(cm_fx6_splash_locations));
  75 }
  76 #endif
  77
  78 #ifdef CONFIG_IMX_HDMI
  79 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  80 {
  81         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  82         imx_setup_hdmi();
  83         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  84         imx_enable_hdmi_phy();
  85 }
  86
  87 static struct display_info_t preset_hdmi_1024X768 = {
  88         .bus    = -1,
  89         .addr   = 0,
  90         .pixfmt = IPU_PIX_FMT_RGB24,
  91         .enable = cm_fx6_enable_hdmi,
  92         .mode   = {
  93                 .name           = "HDMI",
  94                 .refresh        = 60,
  95                 .xres           = 1024,
  96                 .yres           = 768,
  97                 .pixclock       = 40385,
  98                 .left_margin    = 220,
  99                 .right_margin   = 40,
 100                 .upper_margin   = 21,
 101                 .lower_margin   = 7,
 102                 .hsync_len      = 60,
 103                 .vsync_len      = 10,
 104                 .sync           = FB_SYNC_EXT,
 105                 .vmode          = FB_VMODE_NONINTERLACED,
 106         }
 107 };
 108
 109 static void cm_fx6_setup_display(void)
 110 {
 111         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 112
 113         enable_ipu_clock();
 114         clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
 115 }
 116
 117 int board_video_skip(void)
 118 {
 119         int ret;
 120         struct display_info_t *preset;
 121         char const *panel = env_get("displaytype");
 122
 123         if (!panel) /* Also accept panel for backward compatibility */
 124                 panel = env_get("panel");
 125
 126         if (!panel)
 127                 return -ENOENT;
 128
 129         if (!strcmp(panel, "HDMI"))
 130                 preset = &preset_hdmi_1024X768;
 131         else
 132                 return -EINVAL;
 133
 134         ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
 135         if (ret) {
 136                 printf("Can't init display %s: %d\n", preset->mode.name, ret);
 137                 return ret;
 138         }
 139
 140         preset->enable(preset);
 141         printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
 142                preset->mode.yres);
 143
 144         return 0;
 145 }
 146 #else
 147 static inline void cm_fx6_setup_display(void) {}
 148 #endif /* CONFIG_VIDEO_IPUV3 */
 149
 150 int ipu_displays_init(void)
 151 {
 152         return board_video_skip();
 153 }
 154
 155 #ifdef CONFIG_DWC_AHSATA
 156 static int cm_fx6_issd_gpios[] = {
 157         /* The order of the GPIOs in the array is important! */
 158         CM_FX6_SATA_LDO_EN,
 159         CM_FX6_SATA_PHY_SLP,
 160         CM_FX6_SATA_NRSTDLY,
 161         CM_FX6_SATA_PWREN,
 162         CM_FX6_SATA_NSTANDBY1,
 163         CM_FX6_SATA_NSTANDBY2,
 164 };
 165
 166 static void cm_fx6_sata_power(int on)
 167 {
 168         int i;
 169
 170         if (!on) { /* tell the iSSD that the power will be removed */
 171                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
 172                 mdelay(10);
 173         }
 174
 175         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 176                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
 177                 udelay(100);
 178         }
 179
 180         if (!on) /* for compatibility lower the power loss interrupt */
 181                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 182 }
 183
 184 static iomux_v3_cfg_t const sata_pads[] = {
 185         /* SATA PWR */
 186         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 187         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 188         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 189         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 190         /* SATA CTRL */
 191         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 192         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 193         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 194         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 195         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 196 };
 197
 198 static int cm_fx6_setup_issd(void)
 199 {
 200         int ret, i;
 201
 202         SETUP_IOMUX_PADS(sata_pads);
 203
 204         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 205                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
 206                 if (ret)
 207                         return ret;
 208         }
 209
 210         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
 211         if (ret)
 212                 return ret;
 213
 214         return 0;
 215 }
 216
 217 #define CM_FX6_SATA_INIT_RETRIES        10
 218
 219 #else
 220 static int cm_fx6_setup_issd(void) { return 0; }
 221 #endif
 222
 223 #ifdef CONFIG_SYS_I2C_MXC
 224 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 225                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 226                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 227
 228 I2C_PADS(i2c0_pads,
 229          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 230          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 231          IMX_GPIO_NR(3, 21),
 232          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 233          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 234          IMX_GPIO_NR(3, 28));
 235
 236 I2C_PADS(i2c1_pads,
 237          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 238          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 239          IMX_GPIO_NR(4, 12),
 240          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 241          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 242          IMX_GPIO_NR(4, 13));
 243
 244 I2C_PADS(i2c2_pads,
 245          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 246          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 247          IMX_GPIO_NR(1, 3),
 248          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 249          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 250          IMX_GPIO_NR(1, 6));
 251
 252
 253 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 254 {
 255         int ret;
 256
 257         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 258         if (ret)
 259                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 260
 261         return ret;
 262 }
 263
 264 static int cm_fx6_setup_i2c(void)
 265 {
 266         int ret = 0, err;
 267
 268         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 269         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 270         if (err)
 271                 ret = err;
 272         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 273         if (err)
 274                 ret = err;
 275         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 276         if (err)
 277                 ret = err;
 278
 279         return ret;
 280 }
 281 #else
 282 static int cm_fx6_setup_i2c(void) { return 0; }
 283 #endif
 284
 285 #ifdef CONFIG_USB_EHCI_MX6
 286 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 287                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 288                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 289 #define MX6_USBNC_BASEADDR      0x2184800
 290 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 291
 292 static int cm_fx6_setup_usb_host(void)
 293 {
 294         int err;
 295
 296         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 297         if (err)
 298                 return err;
 299
 300         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 301         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 302
 303         return 0;
 304 }
 305
 306 static int cm_fx6_setup_usb_otg(void)
 307 {
 308         int err;
 309         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 310
 311         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 312         if (err) {
 313                 printf("USB OTG pwr gpio request failed: %d\n", err);
 314                 return err;
 315         }
 316
 317         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 318         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 319                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 320         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 321         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 322         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 323 }
 324
 325 int board_usb_phy_mode(int port)
 326 {
 327         return USB_INIT_HOST;
 328 }
 329
 330 int board_ehci_hcd_init(int port)
 331 {
 332         int ret;
 333         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 334
 335         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 336         if (port != 1)
 337                 return 0;
 338
 339         /* Set PWR polarity to match power switch's enable polarity */
 340         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 341         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 342         if (ret)
 343                 return ret;
 344
 345         udelay(10);
 346         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 347         if (ret)
 348                 return ret;
 349
 350         mdelay(1);
 351
 352         return 0;
 353 }
 354
 355 int board_ehci_power(int port, int on)
 356 {
 357         if (port == 0)
 358                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 359
 360         return 0;
 361 }
 362 #else
 363 static int cm_fx6_setup_usb_otg(void) { return 0; }
 364 static int cm_fx6_setup_usb_host(void) { return 0; }
 365 #endif
 366
 367 #ifdef CONFIG_FEC_MXC
 368 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 369                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 370
 371 static int mx6_rgmii_rework(struct phy_device *phydev)
 372 {
 373         unsigned short val;
 374
 375         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 376          * which cause ethernet link down/up issue, so disable SmartEEE
 377          */
 378         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 379         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 380         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 381         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 382         val &= ~(0x1 << 8);
 383         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 384
 385         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 386         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 387         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 388         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 389
 390         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 391         val &= 0xffe3;
 392         val |= 0x18;
 393         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 394
 395         /* introduce tx clock delay */
 396         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 397         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 398         val |= 0x0100;
 399         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 400
 401         return 0;
 402 }
 403
 404 int board_phy_config(struct phy_device *phydev)
 405 {
 406         mx6_rgmii_rework(phydev);
 407
 408         if (phydev->drv->config)
 409                 return phydev->drv->config(phydev);
 410
 411         return 0;
 412 }
 413
 414 static iomux_v3_cfg_t const enet_pads[] = {
 415         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 416         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 417         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 418         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 419         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 420         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 421         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 422         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 423         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 424         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 425         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 426         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 427         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 428         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 429         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 430         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 431                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 432         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 433                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 434         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 435                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 436 };
 437
 438 static int handle_mac_address(char *env_var, uint eeprom_bus)
 439 {
 440         unsigned char enetaddr[6];
 441         int rc;
 442
 443         rc = eth_env_get_enetaddr(env_var, enetaddr);
 444         if (rc)
 445                 return 0;
 446
 447         rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 448         if (rc)
 449                 return rc;
 450
 451         if (!is_valid_ethaddr(enetaddr))
 452                 return -1;
 453
 454         return eth_env_set_enetaddr(env_var, enetaddr);
 455 }
 456
 457 #define SB_FX6_I2C_EEPROM_BUS   0
 458 #define NO_MAC_ADDR             "No MAC address found for %s\n"
 459 int board_eth_init(bd_t *bis)
 460 {
 461         int err;
 462
 463         if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
 464                 printf(NO_MAC_ADDR, "primary NIC");
 465
 466         if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
 467                 printf(NO_MAC_ADDR, "secondary NIC");
 468
 469         SETUP_IOMUX_PADS(enet_pads);
 470         /* phy reset */
 471         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 472         if (err)
 473                 printf("Etnernet NRST gpio request failed: %d\n", err);
 474         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 475         udelay(500);
 476         gpio_set_value(CM_FX6_ENET_NRST, 1);
 477         enable_enet_clk(1);
 478         return cpu_eth_init(bis);
 479 }
 480 #endif
 481
 482 #ifdef CONFIG_NAND_MXS
 483 static iomux_v3_cfg_t const nand_pads[] = {
 484         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 485         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 486         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 487         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 488         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 489         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 490         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 491         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 492         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 493         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 494         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 495         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 496         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 497         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 498 };
 499
 500 static void cm_fx6_setup_gpmi_nand(void)
 501 {
 502         SETUP_IOMUX_PADS(nand_pads);
 503         /* Enable clock roots */
 504         enable_usdhc_clk(1, 3);
 505         enable_usdhc_clk(1, 4);
 506
 507         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 508                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 509                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 510 }
 511 #else
 512 static void cm_fx6_setup_gpmi_nand(void) {}
 513 #endif
 514
 515 #ifdef CONFIG_MXC_SPI
 516 int cm_fx6_setup_ecspi(void)
 517 {
 518         cm_fx6_set_ecspi_iomux();
 519         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 520 }
 521 #else
 522 int cm_fx6_setup_ecspi(void) { return 0; }
 523 #endif
 524
 525 #ifdef CONFIG_OF_BOARD_SETUP
 526 #define USDHC3_PATH     "/soc/aips-bus@02100000/usdhc@02198000/"
 527
 528 static const struct node_info nodes[] = {
 529         /*
 530          * Both entries target the same flash chip. The st,m25p compatible
 531          * is used in the vendor device trees, while upstream uses (the
 532          * documented) jedec,spi-nor compatible.
 533          */
 534         { "st,m25p",    MTD_DEV_TYPE_NOR,       },
 535         { "jedec,spi-nor",      MTD_DEV_TYPE_NOR,       },
 536 };
 537
 538 int ft_board_setup(void *blob, bd_t *bd)
 539 {
 540         u32 baseboard_rev;
 541         int nodeoffset;
 542         uint8_t enetaddr[6];
 543         char baseboard_name[16];
 544         int err;
 545
 546         fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
 547
 548         /* MAC addr */
 549         if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
 550                 fdt_find_and_setprop(blob,
 551                                      "/soc/aips-bus@02100000/ethernet@02188000",
 552                                      "local-mac-address", enetaddr, 6, 1);
 553         }
 554
 555         if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
 556                 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
 557                                      enetaddr, 6, 1);
 558         }
 559
 560         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 561
 562         baseboard_rev = cl_eeprom_get_board_rev(0);
 563         err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
 564         if (err || baseboard_rev == 0)
 565                 return 0; /* Assume not an early revision SB-FX6m baseboard */
 566
 567         if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
 568                 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
 569                 fdt_delprop(blob, nodeoffset, "cd-gpios");
 570                 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
 571                                      NULL, 0, 1);
 572                 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
 573                                      NULL, 0, 1);
 574         }
 575
 576         return 0;
 577 }
 578 #endif
 579
 580 int board_init(void)
 581 {
 582         int ret;
 583
 584         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 585         cm_fx6_setup_gpmi_nand();
 586
 587         ret = cm_fx6_setup_ecspi();
 588         if (ret)
 589                 printf("Warning: ECSPI setup failed: %d\n", ret);
 590
 591         ret = cm_fx6_setup_usb_otg();
 592         if (ret)
 593                 printf("Warning: USB OTG setup failed: %d\n", ret);
 594
 595         ret = cm_fx6_setup_usb_host();
 596         if (ret)
 597                 printf("Warning: USB host setup failed: %d\n", ret);
 598
 599         /*
 600          * cm-fx6 may have iSSD not assembled and in this case it has
 601          * bypasses for a (m)SATA socket on the baseboard. The socketed
 602          * device is not controlled by those GPIOs. So just print a warning
 603          * if the setup fails.
 604          */
 605         ret = cm_fx6_setup_issd();
 606         if (ret)
 607                 printf("Warning: iSSD setup failed: %d\n", ret);
 608
 609         /* Warn on failure but do not abort boot */
 610         ret = cm_fx6_setup_i2c();
 611         if (ret)
 612                 printf("Warning: I2C setup failed: %d\n", ret);
 613
 614         cm_fx6_setup_display();
 615
 616         /* This should be done in the MMC driver when MX6 has a clock driver */
 617 #ifdef CONFIG_FSL_ESDHC_IMX
 618         if (IS_ENABLED(CONFIG_BLK)) {
 619                 int i;
 620
 621                 cm_fx6_set_usdhc_iomux();
 622                 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
 623                         enable_usdhc_clk(1, i);
 624         }
 625 #endif
 626
 627         return 0;
 628 }
 629
 630 int board_late_init(void)
 631 {
 632 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 633         char baseboard_name[16];
 634         int err;
 635
 636         if (is_mx6dq())
 637                 env_set("board_rev", "MX6Q");
 638         else if (is_mx6dl())
 639                 env_set("board_rev", "MX6DL");
 640
 641         err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
 642         if (err)
 643                 return 0;
 644
 645         if (!strncmp("SB-FX6m", baseboard_name, 7))
 646                 env_set("board_name", "Utilite");
 647 #endif
 648         return 0;
 649 }
 650
 651 int checkboard(void)
 652 {
 653         puts("Board: CM-FX6\n");
 654         return 0;
 655 }
 656
 657 int misc_init_r(void)
 658 {
 659         cl_print_pcb_info();
 660
 661         return 0;
 662 }
 663
 664 int dram_init_banksize(void)
 665 {
 666         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 667         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 668
 669         switch (gd->ram_size) {
 670         case 0x10000000: /* DDR_16BIT_256MB */
 671                 gd->bd->bi_dram[0].size = 0x10000000;
 672                 gd->bd->bi_dram[1].size = 0;
 673                 break;
 674         case 0x20000000: /* DDR_32BIT_512MB */
 675                 gd->bd->bi_dram[0].size = 0x20000000;
 676                 gd->bd->bi_dram[1].size = 0;
 677                 break;
 678         case 0x40000000:
 679                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 680                         gd->bd->bi_dram[0].size = 0x20000000;
 681                         gd->bd->bi_dram[1].size = 0x20000000;
 682                 } else { /* DDR_64BIT_1GB */
 683                         gd->bd->bi_dram[0].size = 0x40000000;
 684                         gd->bd->bi_dram[1].size = 0;
 685                 }
 686                 break;
 687         case 0x80000000: /* DDR_64BIT_2GB */
 688                 gd->bd->bi_dram[0].size = 0x40000000;
 689                 gd->bd->bi_dram[1].size = 0x40000000;
 690                 break;
 691         case 0xEFF00000: /* DDR_64BIT_4GB */
 692                 gd->bd->bi_dram[0].size = 0x70000000;
 693                 gd->bd->bi_dram[1].size = 0x7FF00000;
 694                 break;
 695         }
 696
 697         return 0;
 698 }
 699
 700 int dram_init(void)
 701 {
 702         gd->ram_size = imx_ddr_size();
 703         switch (gd->ram_size) {
 704         case 0x10000000:
 705         case 0x20000000:
 706         case 0x40000000:
 707         case 0x80000000:
 708                 break;
 709         case 0xF0000000:
 710                 gd->ram_size -= 0x100000;
 711                 break;
 712         default:
 713                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 714                 return -1;
 715         }
 716
 717         return 0;
 718 }
 719
 720 u32 get_board_rev(void)
 721 {
 722         return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
 723 }
 724
 725 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 726         .reg = (struct mxc_uart *)UART4_BASE,
 727 };
 728
 729 U_BOOT_DEVICE(cm_fx6_serial) = {
 730         .name   = "serial_mxc",
 731         .platdata = &cm_fx6_mxc_serial_plat,
 732 };
 733
 734 #if CONFIG_IS_ENABLED(AHCI)
 735 static int sata_imx_probe(struct udevice *dev)
 736 {
 737         int i, err;
 738
 739         /* Make sure this gpio has logical 0 value */
 740         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 741         udelay(100);
 742         cm_fx6_sata_power(1);
 743
 744         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 745                 err = setup_sata();
 746                 if (err) {
 747                         printf("SATA setup failed: %d\n", err);
 748                         return err;
 749                 }
 750
 751                 udelay(100);
 752
 753                 err = dwc_ahsata_probe(dev);
 754                 if (!err)
 755                         break;
 756
 757                 /* There is no device on the SATA port */
 758                 if (sata_dm_port_status(0, 0) == 0)
 759                         break;
 760
 761                 /* There's a device, but link not established. Retry */
 762                 device_remove(dev, DM_REMOVE_NORMAL);
 763         }
 764
 765         return 0;
 766 }
 767
 768 static int sata_imx_remove(struct udevice *dev)
 769 {
 770         cm_fx6_sata_power(0);
 771         mdelay(250);
 772
 773         return 0;
 774 }
 775
 776 struct ahci_ops sata_imx_ops = {
 777         .port_status = dwc_ahsata_port_status,
 778         .reset  = dwc_ahsata_bus_reset,
 779         .scan   = dwc_ahsata_scan,
 780 };
 781
 782 static const struct udevice_id sata_imx_ids[] = {
 783         { .compatible = "fsl,imx6q-ahci" },
 784         { }
 785 };
 786
 787 U_BOOT_DRIVER(sata_imx) = {
 788         .name           = "dwc_ahci",
 789         .id             = UCLASS_AHCI,
 790         .of_match       = sata_imx_ids,
 791         .ops            = &sata_imx_ops,
 792         .probe          = sata_imx_probe,
 793         .remove         = sata_imx_remove,  /* reset bus to stop it */
 794 };
 795 #endif /* AHCI */