3 * David Purdy <david.c.purdy@gmail.com>
5 * Based on Kirkwood support:
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; If not, see <http://www.gnu.org/licenses/>.
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/kirkwood.h>
31 #include <asm/arch/mpp.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 int board_early_init_f(void)
39 * default gpio configuration
40 * There are maximum 64 gpios controlled through 2 sets of registers
41 * the below configuration configures mainly initial LED status
43 kw_config_gpio(POGO_E02_OE_VAL_LOW,
45 POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
47 /* Multi-Purpose Pins Functionality configuration */
48 u32 kwmpp_config[] = {
69 MPP29_TSMP9, /* USB Power Enable */
70 MPP48_GPIO, /* LED green */
71 MPP49_GPIO, /* LED orange */
74 kirkwood_mpp_conf(kwmpp_config);
80 /* Boot parameters address */
81 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
86 #ifdef CONFIG_RESET_PHY_R
87 /* Configure and initialize PHY */
92 char *name = "egiga0";
94 if (miiphy_set_current_dev(name))
97 /* command to read PHY dev address */
98 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
99 printf("Err..(%s) could not read PHY dev address\n", __func__);
104 * Enable RGMII delay on Tx and Rx for CPU port
105 * Ref: sec 4.7.2 of chip datasheet
107 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
108 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
109 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
110 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
111 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
114 miiphy_reset(name, devadr);
116 debug("88E1116 Initialized on %s\n", name);
118 #endif /* CONFIG_RESET_PHY_R */