3 * David Purdy <david.c.purdy@gmail.com>
5 * Based on Kirkwood support:
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch/mpp.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 int board_early_init_f(void)
25 * default gpio configuration
26 * There are maximum 64 gpios controlled through 2 sets of registers
27 * the below configuration configures mainly initial LED status
29 mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
31 POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
33 /* Multi-Purpose Pins Functionality configuration */
34 static const u32 kwmpp_config[] = {
55 MPP29_TSMP9, /* USB Power Enable */
56 MPP48_GPIO, /* LED green */
57 MPP49_GPIO, /* LED orange */
60 kirkwood_mpp_conf(kwmpp_config, NULL);
66 /* Boot parameters address */
67 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
72 #ifdef CONFIG_RESET_PHY_R
73 /* Configure and initialize PHY */
78 char *name = "egiga0";
80 if (miiphy_set_current_dev(name))
83 /* command to read PHY dev address */
84 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
85 printf("Err..(%s) could not read PHY dev address\n", __func__);
90 * Enable RGMII delay on Tx and Rx for CPU port
91 * Ref: sec 4.7.2 of chip datasheet
93 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
94 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
95 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
96 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
97 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
100 miiphy_reset(name, devadr);
102 debug("88E1116 Initialized on %s\n", name);
104 #endif /* CONFIG_RESET_PHY_R */