board/cirrus/edb93xx/edb93xx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board initialization for EP93xx
   4  *
   5  * Copyright (C) 2013
   6  * Sergey Kostanbaev <sergey.kostanbaev <at> fairwaves.ru>
   7  *
   8  * Copyright (C) 2009
   9  * Matthias Kaehlcke <matthias <at> kaehlcke.net>
  10  *
  11  * (C) Copyright 2002 2003
  12  * Network Audio Technologies, Inc. <www.netaudiotech.com>
  13  * Adam Bezanson <bezanson <at> netaudiotech.com>
  14  */
  15
  16 #include <config.h>
  17 #include <common.h>
  18 #include <cpu_func.h>
  19 #include <irq_func.h>
  20 #include <netdev.h>
  21 #include <status_led.h>
  22 #include <asm/io.h>
  23 #include <asm/mach-types.h>
  24 #include <asm/arch/ep93xx.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /*
  29  * usb_div: 4, nbyp2: 1, pll2_en: 1
  30  * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000,
  31  * pll2_x2: 384000000.000000, pll2_out: 192000000.000000
  32  */
  33 #define CLKSET2_VAL     (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT |  \
  34                         24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT |  \
  35                         24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT |  \
  36                         1 << SYSCON_CLKSET_PLL_PS_SHIFT |       \
  37                         SYSCON_CLKSET2_PLL2_EN |                \
  38                         SYSCON_CLKSET2_NBYP2 |                  \
  39                         3 << SYSCON_CLKSET2_USB_DIV_SHIFT)
  40
  41 #define SMC_BCR6_VALUE  (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \
  42                         SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \
  43                         1 << SMC_BCR_MW_SHIFT)
  44
  45 /* delay execution before timers are initialized */
  46 static inline void early_udelay(uint32_t usecs)
  47 {
  48         /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */
  49         register uint32_t loops = (usecs * 1000) / 20;
  50
  51         __asm__ volatile ("1:\n"
  52                         "subs %0, %1, #1\n"
  53                         "bne 1b" : "=r" (loops) : "0" (loops));
  54 }
  55
  56 #ifndef CONFIG_EP93XX_NO_FLASH_CFG
  57 static void flash_cfg(void)
  58 {
  59         struct smc_regs *smc = (struct smc_regs *)SMC_BASE;
  60
  61         writel(SMC_BCR6_VALUE, &smc->bcr6);
  62 }
  63 #else
  64 #define flash_cfg()
  65 #endif
  66
  67 int board_init(void)
  68 {
  69         /*
  70          * Setup PLL2, PPL1 has been set during lowlevel init
  71          */
  72         struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
  73         writel(CLKSET2_VAL, &syscon->clkset2);
  74
  75         /*
  76          * the user's guide recommends to wait at least 1 ms for PLL2 to
  77          * stabilize
  78          */
  79         early_udelay(1000);
  80
  81         /* Go to Async mode */
  82         __asm__ volatile ("mrc p15, 0, r0, c1, c0, 0");
  83         __asm__ volatile ("orr r0, r0, #0xc0000000");
  84         __asm__ volatile ("mcr p15, 0, r0, c1, c0, 0");
  85
  86         icache_enable();
  87
  88 #ifdef USE_920T_MMU
  89         dcache_enable();
  90 #endif
  91
  92         /* Machine number, as defined in linux/arch/arm/tools/mach-types */
  93         gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
  94
  95         /* adress of boot parameters */
  96         gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
  97
  98         /* We have a console */
  99         gd->have_console = 1;
 100
 101         enable_interrupts();
 102
 103         flash_cfg();
 104
 105         green_led_on();
 106         red_led_off();
 107
 108         return 0;
 109 }
 110
 111 int board_early_init_f(void)
 112 {
 113         /*
 114          * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of
 115          * 14.7456/2 MHz
 116          */
 117         struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
 118         writel(SYSCON_PWRCNT_UART_BAUD, &syscon->pwrcnt);
 119         return 0;
 120 }
 121
 122 int board_eth_init(bd_t *bd)
 123 {
 124         return ep93xx_eth_initialize(0, MAC_BASE);
 125 }
 126
 127 static void dram_fill_bank_addr(unsigned dram_addr_mask, unsigned dram_bank_cnt,
 128                                 unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS])
 129 {
 130         if (dram_bank_cnt == 1) {
 131                 dram_bank_base[0] = PHYS_SDRAM_1;
 132         } else {
 133                 /* Table lookup for holes in address space. Maximum memory
 134                  * for the single SDCS may be up to 256Mb. We start scanning
 135                  * banks from 1Mb, so it could be up to 128 banks theoretically.
 136                  * We need at maximum 7 bits for the loockup, 8 slots is
 137                  * enough for the worst case.
 138                  */
 139                 unsigned tbl[8];
 140                 unsigned i = dram_bank_cnt / 2;
 141                 unsigned j = 0x00100000; /* 1 Mb */
 142                 unsigned *ptbl = tbl;
 143                 do {
 144                         while (!(dram_addr_mask & j)) {
 145                                 j <<= 1;
 146                         }
 147                         *ptbl++ = j;
 148                         j <<= 1;
 149                         i >>= 1;
 150                 } while (i != 0);
 151
 152                 for (i = dram_bank_cnt, j = 0;
 153                      (i != 0) && (j < CONFIG_NR_DRAM_BANKS); --i, ++j) {
 154                         unsigned addr = PHYS_SDRAM_1;
 155                         unsigned k;
 156                         unsigned bit;
 157
 158                         for (k = 0, bit = 1; k < 8; k++, bit <<= 1) {
 159                                 if (bit & j)
 160                                         addr |= tbl[k];
 161                         }
 162
 163                         dram_bank_base[j] = addr;
 164                 }
 165         }
 166 }
 167
 168 /* called in board_init_f (before relocation) */
 169 static unsigned dram_init_banksize_int(int print)
 170 {
 171         /*
 172          * Collect information of banks that has been filled during lowlevel
 173          * initialization
 174          */
 175         unsigned i;
 176         unsigned dram_bank_base[CONFIG_NR_DRAM_BANKS];
 177         unsigned dram_total = 0;
 178         unsigned dram_bank_size = *(unsigned *)
 179                                   (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_SIZE);
 180         unsigned dram_addr_mask = *(unsigned *)
 181                                   (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_MASK);
 182         unsigned dram_bank_cnt = *(unsigned *)
 183                                  (PHYS_SDRAM_1 | UBOOT_MEMORYCNF_BANK_COUNT);
 184
 185         dram_fill_bank_addr(dram_addr_mask, dram_bank_cnt, dram_bank_base);
 186
 187         for (i = 0; i < dram_bank_cnt; i++) {
 188                 gd->bd->bi_dram[i].start = dram_bank_base[i];
 189                 gd->bd->bi_dram[i].size = dram_bank_size;
 190                 dram_total += dram_bank_size;
 191         }
 192         for (; i < CONFIG_NR_DRAM_BANKS; i++) {
 193                 gd->bd->bi_dram[i].start = 0;
 194                 gd->bd->bi_dram[i].size = 0;
 195         }
 196
 197         if (print) {
 198                 printf("DRAM mask: %08x\n", dram_addr_mask);
 199                 printf("DRAM total %u banks:\n", dram_bank_cnt);
 200                 printf("bank          base-address          size\n");
 201
 202                 if (dram_bank_cnt > CONFIG_NR_DRAM_BANKS) {
 203                         printf("WARNING! UBoot was configured for %u banks,\n"
 204                                 "but %u has been found. "
 205                                 "Supressing extra memory banks\n",
 206                                  CONFIG_NR_DRAM_BANKS, dram_bank_cnt);
 207                         dram_bank_cnt = CONFIG_NR_DRAM_BANKS;
 208                 }
 209
 210                 for (i = 0; i < dram_bank_cnt; i++) {
 211                         printf("  %u             %08x            %08x\n",
 212                                i, dram_bank_base[i], dram_bank_size);
 213                 }
 214                 printf("  ------------------------------------------\n"
 215                         "Total                              %9d\n\n",
 216                         dram_total);
 217         }
 218
 219         return dram_total;
 220 }
 221
 222 int dram_init_banksize(void)
 223 {
 224         dram_init_banksize_int(0);
 225
 226         return 0;
 227 }
 228
 229 /* called in board_init_f (before relocation) */
 230 int dram_init(void)
 231 {
 232         struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
 233         unsigned sec_id = readl(SECURITY_EXTENSIONID);
 234         unsigned chip_id = readl(&syscon->chipid);
 235
 236         printf("CPU: Cirrus Logic ");
 237         switch (sec_id & 0x000001FE) {
 238         case 0x00000008:
 239                 printf("EP9301");
 240                 break;
 241         case 0x00000004:
 242                 printf("EP9307");
 243                 break;
 244         case 0x00000002:
 245                 printf("EP931x");
 246                 break;
 247         case 0x00000000:
 248                 printf("EP9315");
 249                 break;
 250         default:
 251                 printf("<unknown>");
 252                 break;
 253         }
 254
 255         printf(" - Rev. ");
 256         switch (chip_id & 0xF0000000) {
 257         case 0x00000000:
 258                 printf("A");
 259                 break;
 260         case 0x10000000:
 261                 printf("B");
 262                 break;
 263         case 0x20000000:
 264                 printf("C");
 265                 break;
 266         case 0x30000000:
 267                 printf("D0");
 268                 break;
 269         case 0x40000000:
 270                 printf("D1");
 271                 break;
 272         case 0x50000000:
 273                 printf("E0");
 274                 break;
 275         case 0x60000000:
 276                 printf("E1");
 277                 break;
 278         case 0x70000000:
 279                 printf("E2");
 280                 break;
 281         default:
 282                 printf("?");
 283                 break;
 284         }
 285         printf(" (SecExtID=%.8x/ChipID=%.8x)\n", sec_id, chip_id);
 286
 287         gd->ram_size = dram_init_banksize_int(1);
 288         return 0;
 289 }