board/cavium/thunderx/thunderx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /**
   3  * (C) Copyright 2014, Cavium Inc.
   4 **/
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <malloc.h>
  11 #include <errno.h>
  12 #include <linux/compiler.h>
  13
  14 #include <cavium/atf.h>
  15 #include <asm/armv8/mmu.h>
  16
  17 #if !CONFIG_IS_ENABLED(OF_CONTROL)
  18 #include <dm/platform_data/serial_pl01x.h>
  19
  20 static const struct pl01x_serial_platdata serial0 = {
  21         .base = CONFIG_SYS_SERIAL0,
  22         .type = TYPE_PL011,
  23         .clock = 0,
  24         .skip_init = true,
  25 };
  26
  27 U_BOOT_DEVICE(thunderx_serial0) = {
  28         .name = "serial_pl01x",
  29         .platdata = &serial0,
  30 };
  31
  32 static const struct pl01x_serial_platdata serial1 = {
  33         .base = CONFIG_SYS_SERIAL1,
  34         .type = TYPE_PL011,
  35         .clock = 0,
  36         .skip_init = true,
  37 };
  38
  39 U_BOOT_DEVICE(thunderx_serial1) = {
  40         .name = "serial_pl01x",
  41         .platdata = &serial1,
  42 };
  43 #endif
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 static struct mm_region thunderx_mem_map[] = {
  48         {
  49                 .virt = 0x000000000000UL,
  50                 .phys = 0x000000000000UL,
  51                 .size = 0x40000000000UL,
  52                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
  53         }, {
  54                 .virt = 0x800000000000UL,
  55                 .phys = 0x800000000000UL,
  56                 .size = 0x40000000000UL,
  57                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  58                          PTE_BLOCK_NON_SHARE,
  59         }, {
  60                 .virt = 0x840000000000UL,
  61                 .phys = 0x840000000000UL,
  62                 .size = 0x40000000000UL,
  63                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  64                          PTE_BLOCK_NON_SHARE,
  65         }, {
  66                 /* List terminator */
  67                 0,
  68         }
  69 };
  70
  71 struct mm_region *mem_map = thunderx_mem_map;
  72
  73 int board_init(void)
  74 {
  75         return 0;
  76 }
  77
  78 int timer_init(void)
  79 {
  80         return 0;
  81 }
  82
  83 int dram_init(void)
  84 {
  85         ssize_t node_count = atf_node_count();
  86         ssize_t dram_size;
  87         int node;
  88
  89         printf("Initializing\nNodes in system: %zd\n", node_count);
  90
  91         gd->ram_size = 0;
  92
  93         for (node = 0; node < node_count; node++) {
  94                 dram_size = atf_dram_size(node);
  95                 printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
  96                 gd->ram_size += dram_size;
  97         }
  98
  99         gd->ram_size -= MEM_BASE;
 100
 101         *(unsigned long *)CPU_RELEASE_ADDR = 0;
 102
 103         puts("DRAM size:");
 104
 105         return 0;
 106 }
 107
 108 /*
 109  * Board specific reset that is system reset.
 110  */
 111 void reset_cpu(ulong addr)
 112 {
 113 }
 114
 115 /*
 116  * Board specific ethernet initialization routine.
 117  */
 118 int board_eth_init(bd_t *bis)
 119 {
 120         int rc = 0;
 121
 122         return rc;
 123 }
 124
 125 #ifdef CONFIG_PCI
 126 void pci_init_board(void)
 127 {
 128         printf("DEBUG: PCI Init TODO *****\n");
 129 }
 130 #endif