3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /*****************************************************************************
32 * initialize SDRAM/DDRAM controller.
33 * TBD: get data from I2C EEPROM
34 *****************************************************************************/
35 long int initdram (int board_type)
44 #define MODE_EN 0x80000000
48 /* configure SDRAM start/end */
49 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
50 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x8000000;
52 /* setup config registers */
53 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
54 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
56 /* unlock mode register */
57 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
58 /* precharge all banks */
59 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
61 /* set extended mode register */
62 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
64 /* set mode register */
65 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
66 /* precharge all banks */
67 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
69 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
70 /* set mode register */
71 *(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
72 /* normal operation */
73 *(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
74 /* write default TAP delay */
75 *(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
77 #endif /* CFG_RAMBOOT */
79 dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20) +
80 ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS1CFG - 0x13)) << 20);
82 /* return total ram size */
86 /*****************************************************************************
87 * print board identification
88 *****************************************************************************/
91 puts ("Board: CANMB\n");
95 int board_early_init_r (void)
97 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
98 *(vu_long *)MPC5XXX_BOOTCS_START =
99 *(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
100 *(vu_long *)MPC5XXX_BOOTCS_STOP =
101 *(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);