board/boundary/nitrogen6x/nitrogen6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   4  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <net.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/sys_proto.h>
  15 #include <malloc.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <linux/errno.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/sata.h>
  22 #include <asm/mach-imx/spi.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24 #include <asm/mach-imx/video.h>
  25 #include <mmc.h>
  26 #include <fsl_esdhc_imx.h>
  27 #include <micrel.h>
  28 #include <miiphy.h>
  29 #include <netdev.h>
  30 #include <asm/arch/crm_regs.h>
  31 #include <asm/arch/mxc_hdmi.h>
  32 #include <i2c.h>
  33 #include <input.h>
  34 #include <netdev.h>
  35 #include <usb/ehci-ci.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  39
  40 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  41         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  42         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  43
  44 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  45         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  46         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  47
  48 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  49         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  50
  51 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |         \
  52         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  53
  54 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |                  \
  55         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  56
  57 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  58         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  59         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  60
  61 #define RGB_PAD_CTRL    PAD_CTL_DSE_120ohm
  62
  63 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
  64         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  65         PAD_CTL_SRE_SLOW)
  66
  67 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
  68         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  69         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  70
  71 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  72
  73 /* Prevent compiler error if gpio number 08 or 09 is used */
  74 #define not_octal(gp) ((((0x##gp >> 4) & 0xf) * 10) + ((0x##gp & 0xf)))
  75
  76 #define _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,             \
  77                 sda_pad, sda_bank, sda_gp, pad_ctrl, join_io) {                \
  78         .scl = {                                                               \
  79                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##scl_pad##__##i2cnum##_SCL,\
  80                                          pad_ctrl),                            \
  81                 .gpio_mode = NEW_PAD_CTRL(                                     \
  82                         cpu##_PAD_##scl_pad##__GPIO##scl_bank##join_io##scl_gp,\
  83                         pad_ctrl),                                             \
  84                 .gp = IMX_GPIO_NR(scl_bank, not_octal(scl_gp))                 \
  85         },                                                                     \
  86         .sda = {                                                               \
  87                 .i2c_mode = NEW_PAD_CTRL(cpu##_PAD_##sda_pad##__##i2cnum##_SDA,\
  88                                          pad_ctrl),                            \
  89                 .gpio_mode = NEW_PAD_CTRL(                                     \
  90                         cpu##_PAD_##sda_pad##__GPIO##sda_bank##join_io##sda_gp,\
  91                         pad_ctrl),                                             \
  92                         .gp = IMX_GPIO_NR(sda_bank, not_octal(sda_gp))         \
  93         }                                                                      \
  94 }
  95
  96 #define I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,              \
  97                 sda_pad, sda_bank, sda_gp, pad_ctrl)                           \
  98                 _I2C_PADS_INFO_CPU(cpu, i2cnum, scl_pad, scl_bank, scl_gp,     \
  99                                 sda_pad, sda_bank, sda_gp, pad_ctrl, _IO)
 100
 101 #if defined(CONFIG_MX6QDL)
 102 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 103                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 104         I2C_PADS_INFO_CPU(MX6Q, i2cnum, scl_pad, scl_bank, scl_gp,      \
 105                 sda_pad, sda_bank, sda_gp, pad_ctrl),                   \
 106         I2C_PADS_INFO_CPU(MX6DL, i2cnum, scl_pad, scl_bank, scl_gp,     \
 107                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 108 #define I2C_PADS_INFO_ENTRY_SPACING 2
 109
 110 #define IOMUX_PAD_CTRL(name, pad_ctrl) \
 111                 NEW_PAD_CTRL(MX6Q_PAD_##name, pad_ctrl),        \
 112                 NEW_PAD_CTRL(MX6DL_PAD_##name, pad_ctrl)
 113 #else
 114 #define I2C_PADS_INFO_ENTRY(i2cnum, scl_pad, scl_bank, scl_gp,          \
 115                 sda_pad, sda_bank, sda_gp, pad_ctrl)                    \
 116         I2C_PADS_INFO_CPU(MX6, i2cnum, scl_pad, scl_bank, scl_gp,       \
 117                 sda_pad, sda_bank, sda_gp, pad_ctrl)
 118 #define I2C_PADS_INFO_ENTRY_SPACING 1
 119
 120 #define IOMUX_PAD_CTRL(name, pad_ctrl) NEW_PAD_CTRL(MX6_PAD_##name, pad_ctrl)
 121 #endif
 122
 123 int dram_init(void)
 124 {
 125         gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 126
 127         return 0;
 128 }
 129
 130 static iomux_v3_cfg_t const uart1_pads[] = {
 131         IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
 132         IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
 133 };
 134
 135 static iomux_v3_cfg_t const uart2_pads[] = {
 136         IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
 137         IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
 138 };
 139
 140 static struct i2c_pads_info i2c_pads[] = {
 141         /* I2C1, SGTL5000 */
 142         I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
 143         /* I2C2 Camera, MIPI */
 144         I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13,
 145                             I2C_PAD_CTRL),
 146         /* I2C3, J15 - RGB connector */
 147         I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
 148 };
 149
 150 #define I2C_BUS_CNT    3
 151
 152 static iomux_v3_cfg_t const usdhc2_pads[] = {
 153         IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
 154         IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
 155         IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
 156         IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
 157         IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
 158         IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
 159 };
 160
 161 static iomux_v3_cfg_t const usdhc3_pads[] = {
 162         IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
 163         IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
 164         IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
 165         IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
 166         IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
 167         IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
 168         IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, NO_PAD_CTRL), /* CD */
 169 };
 170
 171 static iomux_v3_cfg_t const usdhc4_pads[] = {
 172         IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
 173         IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
 174         IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
 175         IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
 176         IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
 177         IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
 178         IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, NO_PAD_CTRL), /* CD */
 179 };
 180
 181 static iomux_v3_cfg_t const enet_pads1[] = {
 182         IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
 183         IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
 184         IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, ENET_PAD_CTRL),
 185         IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, ENET_PAD_CTRL),
 186         IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, ENET_PAD_CTRL),
 187         IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, ENET_PAD_CTRL),
 188         IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, ENET_PAD_CTRL),
 189         IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, ENET_PAD_CTRL),
 190         IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, ENET_PAD_CTRL),
 191         /* pin 35 - 1 (PHY_AD2) on reset */
 192         IOMUX_PAD_CTRL(RGMII_RXC__GPIO6_IO30, NO_PAD_CTRL),
 193         /* pin 32 - 1 - (MODE0) all */
 194         IOMUX_PAD_CTRL(RGMII_RD0__GPIO6_IO25, NO_PAD_CTRL),
 195         /* pin 31 - 1 - (MODE1) all */
 196         IOMUX_PAD_CTRL(RGMII_RD1__GPIO6_IO27, NO_PAD_CTRL),
 197         /* pin 28 - 1 - (MODE2) all */
 198         IOMUX_PAD_CTRL(RGMII_RD2__GPIO6_IO28, NO_PAD_CTRL),
 199         /* pin 27 - 1 - (MODE3) all */
 200         IOMUX_PAD_CTRL(RGMII_RD3__GPIO6_IO29, NO_PAD_CTRL),
 201         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 202         IOMUX_PAD_CTRL(RGMII_RX_CTL__GPIO6_IO24, NO_PAD_CTRL),
 203         /* pin 42 PHY nRST */
 204         IOMUX_PAD_CTRL(EIM_D23__GPIO3_IO23, NO_PAD_CTRL),
 205         IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, NO_PAD_CTRL),
 206 };
 207
 208 static iomux_v3_cfg_t const enet_pads2[] = {
 209         IOMUX_PAD_CTRL(RGMII_RXC__RGMII_RXC, ENET_PAD_CTRL),
 210         IOMUX_PAD_CTRL(RGMII_RD0__RGMII_RD0, ENET_PAD_CTRL),
 211         IOMUX_PAD_CTRL(RGMII_RD1__RGMII_RD1, ENET_PAD_CTRL),
 212         IOMUX_PAD_CTRL(RGMII_RD2__RGMII_RD2, ENET_PAD_CTRL),
 213         IOMUX_PAD_CTRL(RGMII_RD3__RGMII_RD3, ENET_PAD_CTRL),
 214         IOMUX_PAD_CTRL(RGMII_RX_CTL__RGMII_RX_CTL, ENET_PAD_CTRL),
 215 };
 216
 217 static iomux_v3_cfg_t const misc_pads[] = {
 218         IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
 219         IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
 220         IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
 221         /* OTG Power enable */
 222         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 223 };
 224
 225 /* wl1271 pads on nitrogen6x */
 226 static iomux_v3_cfg_t const wl12xx_pads[] = {
 227         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 228         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 229         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 230 };
 231 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 232 #define WL12XX_WL_ENABLE_GP     IMX_GPIO_NR(6, 15)
 233 #define WL12XX_BT_ENABLE_GP     IMX_GPIO_NR(6, 16)
 234
 235 /* Button assignments for J14 */
 236 static iomux_v3_cfg_t const button_pads[] = {
 237         /* Menu */
 238         IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
 239         /* Back */
 240         IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
 241         /* Labelled Search (mapped to Power under Android) */
 242         IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
 243         /* Home */
 244         IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
 245         /* Volume Down */
 246         IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
 247         /* Volume Up */
 248         IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
 249 };
 250
 251 static void setup_iomux_enet(void)
 252 {
 253         gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
 254         gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
 255         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 256         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 257         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 258         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 259         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 260         SETUP_IOMUX_PADS(enet_pads1);
 261         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 262
 263         /* Need delay 10ms according to KSZ9021 spec */
 264         udelay(1000 * 10);
 265         gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
 266         gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
 267
 268         SETUP_IOMUX_PADS(enet_pads2);
 269         udelay(100);    /* Wait 100 us before using mii interface */
 270 }
 271
 272 static iomux_v3_cfg_t const usb_pads[] = {
 273         IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, NO_PAD_CTRL),
 274 };
 275
 276 static void setup_iomux_uart(void)
 277 {
 278         SETUP_IOMUX_PADS(uart1_pads);
 279         SETUP_IOMUX_PADS(uart2_pads);
 280 }
 281
 282 #ifdef CONFIG_USB_EHCI_MX6
 283 int board_ehci_hcd_init(int port)
 284 {
 285         SETUP_IOMUX_PADS(usb_pads);
 286
 287         /* Reset USB hub */
 288         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 289         mdelay(2);
 290         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 291
 292         return 0;
 293 }
 294
 295 int board_ehci_power(int port, int on)
 296 {
 297         if (port)
 298                 return 0;
 299         gpio_set_value(GP_USB_OTG_PWR, on);
 300         return 0;
 301 }
 302
 303 #endif
 304
 305 #ifdef CONFIG_FSL_ESDHC_IMX
 306 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 307         {USDHC3_BASE_ADDR},
 308         {USDHC4_BASE_ADDR},
 309 };
 310
 311 int board_mmc_getcd(struct mmc *mmc)
 312 {
 313         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 314         int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
 315                         IMX_GPIO_NR(2, 6);
 316
 317         gpio_direction_input(gp_cd);
 318         return !gpio_get_value(gp_cd);
 319 }
 320
 321 int board_mmc_init(bd_t *bis)
 322 {
 323         int ret;
 324         u32 index = 0;
 325
 326         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 327         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 328
 329         usdhc_cfg[0].max_bus_width = 4;
 330         usdhc_cfg[1].max_bus_width = 4;
 331
 332         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 333                 switch (index) {
 334                 case 0:
 335                         SETUP_IOMUX_PADS(usdhc3_pads);
 336                         break;
 337                 case 1:
 338                        SETUP_IOMUX_PADS(usdhc4_pads);
 339                        break;
 340                 default:
 341                        printf("Warning: you configured more USDHC controllers"
 342                                "(%d) then supported by the board (%d)\n",
 343                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 344                        return -EINVAL;
 345                 }
 346
 347                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 348                 if (ret)
 349                         return ret;
 350         }
 351
 352         return 0;
 353 }
 354 #endif
 355
 356 #ifdef CONFIG_MXC_SPI
 357 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 358 {
 359         return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
 360 }
 361
 362 static iomux_v3_cfg_t const ecspi1_pads[] = {
 363         /* SS1 */
 364         IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, NO_PAD_CTRL),
 365         IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
 366         IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
 367         IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
 368 };
 369
 370 static void setup_spi(void)
 371 {
 372         SETUP_IOMUX_PADS(ecspi1_pads);
 373 }
 374 #endif
 375
 376 int board_phy_config(struct phy_device *phydev)
 377 {
 378         /* min rx data delay */
 379         ksz9021_phy_extended_write(phydev,
 380                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 381         /* min tx data delay */
 382         ksz9021_phy_extended_write(phydev,
 383                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 384         /* max rx/tx clock delay, min rx/tx control */
 385         ksz9021_phy_extended_write(phydev,
 386                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 387         if (phydev->drv->config)
 388                 phydev->drv->config(phydev);
 389
 390         return 0;
 391 }
 392
 393 int board_eth_init(bd_t *bis)
 394 {
 395         uint32_t base = IMX_FEC_BASE;
 396         struct mii_dev *bus = NULL;
 397         struct phy_device *phydev = NULL;
 398         int ret;
 399
 400         gpio_request(WL12XX_WL_IRQ_GP, "wifi_irq");
 401         gpio_request(IMX_GPIO_NR(6, 30), "rgmii_rxc");
 402         gpio_request(IMX_GPIO_NR(6, 25), "rgmii_rd0");
 403         gpio_request(IMX_GPIO_NR(6, 27), "rgmii_rd1");
 404         gpio_request(IMX_GPIO_NR(6, 28), "rgmii_rd2");
 405         gpio_request(IMX_GPIO_NR(6, 29), "rgmii_rd3");
 406         gpio_request(IMX_GPIO_NR(6, 24), "rgmii_rx_ctl");
 407         gpio_request(IMX_GPIO_NR(3, 23), "rgmii_reset_sabrelite");
 408         gpio_request(IMX_GPIO_NR(1, 27), "rgmii_reset_nitrogen6x");
 409         setup_iomux_enet();
 410
 411 #ifdef CONFIG_FEC_MXC
 412         bus = fec_get_miibus(base, -1);
 413         if (!bus)
 414                 return -EINVAL;
 415         /* scan phy 4,5,6,7 */
 416         phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
 417         if (!phydev) {
 418                 ret = -EINVAL;
 419                 goto free_bus;
 420         }
 421         printf("using phy at %d\n", phydev->addr);
 422         ret  = fec_probe(bis, -1, base, bus, phydev);
 423         if (ret)
 424                 goto free_phydev;
 425 #endif
 426
 427 #ifdef CONFIG_CI_UDC
 428         /* For otg ethernet*/
 429         usb_eth_initialize(bis);
 430 #endif
 431         return 0;
 432
 433 free_phydev:
 434         free(phydev);
 435 free_bus:
 436         free(bus);
 437         return ret;
 438 }
 439
 440 static void setup_buttons(void)
 441 {
 442         SETUP_IOMUX_PADS(button_pads);
 443 }
 444
 445 #if defined(CONFIG_VIDEO_IPUV3)
 446
 447 static iomux_v3_cfg_t const backlight_pads[] = {
 448         /* Backlight on RGB connector: J15 */
 449         IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, NO_PAD_CTRL),
 450 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 451
 452         /* Backlight on LVDS connector: J6 */
 453         IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, NO_PAD_CTRL),
 454 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 455 };
 456
 457 static iomux_v3_cfg_t const rgb_pads[] = {
 458         IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
 459         IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),
 460         IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),
 461         IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),
 462         IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, RGB_PAD_CTRL),
 463         IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
 464         IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
 465         IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
 466         IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
 467         IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
 468         IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
 469         IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
 470         IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
 471         IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
 472         IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
 473         IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
 474         IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
 475         IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
 476         IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
 477         IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
 478         IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
 479         IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
 480         IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
 481         IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
 482         IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
 483         IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
 484         IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
 485         IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
 486         IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
 487 };
 488
 489 static void do_enable_hdmi(struct display_info_t const *dev)
 490 {
 491         imx_enable_hdmi_phy();
 492 }
 493
 494 static int detect_i2c(struct display_info_t const *dev)
 495 {
 496         return ((0 == i2c_set_bus_num(dev->bus))
 497                 &&
 498                 (0 == i2c_probe(dev->addr)));
 499 }
 500
 501 static void enable_lvds(struct display_info_t const *dev)
 502 {
 503         struct iomuxc *iomux = (struct iomuxc *)
 504                                 IOMUXC_BASE_ADDR;
 505         u32 reg = readl(&iomux->gpr[2]);
 506         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 507         writel(reg, &iomux->gpr[2]);
 508         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 509 }
 510
 511 static void enable_lvds_jeida(struct display_info_t const *dev)
 512 {
 513         struct iomuxc *iomux = (struct iomuxc *)
 514                                 IOMUXC_BASE_ADDR;
 515         u32 reg = readl(&iomux->gpr[2]);
 516         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 517              |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
 518         writel(reg, &iomux->gpr[2]);
 519         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 520 }
 521
 522 static void enable_rgb(struct display_info_t const *dev)
 523 {
 524         SETUP_IOMUX_PADS(rgb_pads);
 525         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 526 }
 527
 528 struct display_info_t const displays[] = {{
 529         .bus    = 1,
 530         .addr   = 0x50,
 531         .pixfmt = IPU_PIX_FMT_RGB24,
 532         .detect = detect_i2c,
 533         .enable = do_enable_hdmi,
 534         .mode   = {
 535                 .name           = "HDMI",
 536                 .refresh        = 60,
 537                 .xres           = 1024,
 538                 .yres           = 768,
 539                 .pixclock       = 15385,
 540                 .left_margin    = 220,
 541                 .right_margin   = 40,
 542                 .upper_margin   = 21,
 543                 .lower_margin   = 7,
 544                 .hsync_len      = 60,
 545                 .vsync_len      = 10,
 546                 .sync           = FB_SYNC_EXT,
 547                 .vmode          = FB_VMODE_NONINTERLACED
 548 } }, {
 549         .bus    = 0,
 550         .addr   = 0,
 551         .pixfmt = IPU_PIX_FMT_RGB24,
 552         .detect = NULL,
 553         .enable = enable_lvds_jeida,
 554         .mode   = {
 555                 .name           = "LDB-WXGA",
 556                 .refresh        = 60,
 557                 .xres           = 1280,
 558                 .yres           = 800,
 559                 .pixclock       = 14065,
 560                 .left_margin    = 40,
 561                 .right_margin   = 40,
 562                 .upper_margin   = 3,
 563                 .lower_margin   = 80,
 564                 .hsync_len      = 10,
 565                 .vsync_len      = 10,
 566                 .sync           = FB_SYNC_EXT,
 567                 .vmode          = FB_VMODE_NONINTERLACED
 568 } }, {
 569         .bus    = 0,
 570         .addr   = 0,
 571         .pixfmt = IPU_PIX_FMT_RGB24,
 572         .detect = NULL,
 573         .enable = enable_lvds,
 574         .mode   = {
 575                 .name           = "LDB-WXGA-S",
 576                 .refresh        = 60,
 577                 .xres           = 1280,
 578                 .yres           = 800,
 579                 .pixclock       = 14065,
 580                 .left_margin    = 40,
 581                 .right_margin   = 40,
 582                 .upper_margin   = 3,
 583                 .lower_margin   = 80,
 584                 .hsync_len      = 10,
 585                 .vsync_len      = 10,
 586                 .sync           = FB_SYNC_EXT,
 587                 .vmode          = FB_VMODE_NONINTERLACED
 588 } }, {
 589         .bus    = 2,
 590         .addr   = 0x4,
 591         .pixfmt = IPU_PIX_FMT_LVDS666,
 592         .detect = detect_i2c,
 593         .enable = enable_lvds,
 594         .mode   = {
 595                 .name           = "Hannstar-XGA",
 596                 .refresh        = 60,
 597                 .xres           = 1024,
 598                 .yres           = 768,
 599                 .pixclock       = 15385,
 600                 .left_margin    = 220,
 601                 .right_margin   = 40,
 602                 .upper_margin   = 21,
 603                 .lower_margin   = 7,
 604                 .hsync_len      = 60,
 605                 .vsync_len      = 10,
 606                 .sync           = FB_SYNC_EXT,
 607                 .vmode          = FB_VMODE_NONINTERLACED
 608 } }, {
 609         .bus    = 0,
 610         .addr   = 0,
 611         .pixfmt = IPU_PIX_FMT_LVDS666,
 612         .detect = NULL,
 613         .enable = enable_lvds,
 614         .mode   = {
 615                 .name           = "LG-9.7",
 616                 .refresh        = 60,
 617                 .xres           = 1024,
 618                 .yres           = 768,
 619                 .pixclock       = 15385, /* ~65MHz */
 620                 .left_margin    = 480,
 621                 .right_margin   = 260,
 622                 .upper_margin   = 16,
 623                 .lower_margin   = 6,
 624                 .hsync_len      = 250,
 625                 .vsync_len      = 10,
 626                 .sync           = FB_SYNC_EXT,
 627                 .vmode          = FB_VMODE_NONINTERLACED
 628 } }, {
 629         .bus    = 2,
 630         .addr   = 0x38,
 631         .pixfmt = IPU_PIX_FMT_LVDS666,
 632         .detect = detect_i2c,
 633         .enable = enable_lvds,
 634         .mode   = {
 635                 .name           = "wsvga-lvds",
 636                 .refresh        = 60,
 637                 .xres           = 1024,
 638                 .yres           = 600,
 639                 .pixclock       = 15385,
 640                 .left_margin    = 220,
 641                 .right_margin   = 40,
 642                 .upper_margin   = 21,
 643                 .lower_margin   = 7,
 644                 .hsync_len      = 60,
 645                 .vsync_len      = 10,
 646                 .sync           = FB_SYNC_EXT,
 647                 .vmode          = FB_VMODE_NONINTERLACED
 648 } }, {
 649         .bus    = 2,
 650         .addr   = 0x10,
 651         .pixfmt = IPU_PIX_FMT_RGB666,
 652         .detect = detect_i2c,
 653         .enable = enable_rgb,
 654         .mode   = {
 655                 .name           = "fusion7",
 656                 .refresh        = 60,
 657                 .xres           = 800,
 658                 .yres           = 480,
 659                 .pixclock       = 33898,
 660                 .left_margin    = 96,
 661                 .right_margin   = 24,
 662                 .upper_margin   = 3,
 663                 .lower_margin   = 10,
 664                 .hsync_len      = 72,
 665                 .vsync_len      = 7,
 666                 .sync           = 0x40000002,
 667                 .vmode          = FB_VMODE_NONINTERLACED
 668 } }, {
 669         .bus    = 0,
 670         .addr   = 0,
 671         .pixfmt = IPU_PIX_FMT_RGB666,
 672         .detect = NULL,
 673         .enable = enable_rgb,
 674         .mode   = {
 675                 .name           = "svga",
 676                 .refresh        = 60,
 677                 .xres           = 800,
 678                 .yres           = 600,
 679                 .pixclock       = 15385,
 680                 .left_margin    = 220,
 681                 .right_margin   = 40,
 682                 .upper_margin   = 21,
 683                 .lower_margin   = 7,
 684                 .hsync_len      = 60,
 685                 .vsync_len      = 10,
 686                 .sync           = 0,
 687                 .vmode          = FB_VMODE_NONINTERLACED
 688 } }, {
 689         .bus    = 2,
 690         .addr   = 0x41,
 691         .pixfmt = IPU_PIX_FMT_LVDS666,
 692         .detect = detect_i2c,
 693         .enable = enable_lvds,
 694         .mode   = {
 695                 .name           = "amp1024x600",
 696                 .refresh        = 60,
 697                 .xres           = 1024,
 698                 .yres           = 600,
 699                 .pixclock       = 15385,
 700                 .left_margin    = 220,
 701                 .right_margin   = 40,
 702                 .upper_margin   = 21,
 703                 .lower_margin   = 7,
 704                 .hsync_len      = 60,
 705                 .vsync_len      = 10,
 706                 .sync           = FB_SYNC_EXT,
 707                 .vmode          = FB_VMODE_NONINTERLACED
 708 } }, {
 709         .bus    = 0,
 710         .addr   = 0,
 711         .pixfmt = IPU_PIX_FMT_LVDS666,
 712         .detect = 0,
 713         .enable = enable_lvds,
 714         .mode   = {
 715                 .name           = "wvga-lvds",
 716                 .refresh        = 57,
 717                 .xres           = 800,
 718                 .yres           = 480,
 719                 .pixclock       = 15385,
 720                 .left_margin    = 220,
 721                 .right_margin   = 40,
 722                 .upper_margin   = 21,
 723                 .lower_margin   = 7,
 724                 .hsync_len      = 60,
 725                 .vsync_len      = 10,
 726                 .sync           = FB_SYNC_EXT,
 727                 .vmode          = FB_VMODE_NONINTERLACED
 728 } }, {
 729         .bus    = 2,
 730         .addr   = 0x48,
 731         .pixfmt = IPU_PIX_FMT_RGB666,
 732         .detect = detect_i2c,
 733         .enable = enable_rgb,
 734         .mode   = {
 735                 .name           = "wvga-rgb",
 736                 .refresh        = 57,
 737                 .xres           = 800,
 738                 .yres           = 480,
 739                 .pixclock       = 37037,
 740                 .left_margin    = 40,
 741                 .right_margin   = 60,
 742                 .upper_margin   = 10,
 743                 .lower_margin   = 10,
 744                 .hsync_len      = 20,
 745                 .vsync_len      = 10,
 746                 .sync           = 0,
 747                 .vmode          = FB_VMODE_NONINTERLACED
 748 } }, {
 749         .bus    = 0,
 750         .addr   = 0,
 751         .pixfmt = IPU_PIX_FMT_RGB24,
 752         .detect = NULL,
 753         .enable = enable_rgb,
 754         .mode   = {
 755                 .name           = "qvga",
 756                 .refresh        = 60,
 757                 .xres           = 320,
 758                 .yres           = 240,
 759                 .pixclock       = 37037,
 760                 .left_margin    = 38,
 761                 .right_margin   = 37,
 762                 .upper_margin   = 16,
 763                 .lower_margin   = 15,
 764                 .hsync_len      = 30,
 765                 .vsync_len      = 3,
 766                 .sync           = 0,
 767                 .vmode          = FB_VMODE_NONINTERLACED
 768 } } };
 769 size_t display_count = ARRAY_SIZE(displays);
 770
 771 int board_cfb_skip(void)
 772 {
 773         return NULL != env_get("novideo");
 774 }
 775
 776 static void setup_display(void)
 777 {
 778         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 779         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 780         int reg;
 781
 782         enable_ipu_clock();
 783         imx_setup_hdmi();
 784         /* Turn on LDB0,IPU,IPU DI0 clocks */
 785         reg = __raw_readl(&mxc_ccm->CCGR3);
 786         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK;
 787         writel(reg, &mxc_ccm->CCGR3);
 788
 789         /* set LDB0, LDB1 clk select to 011/011 */
 790         reg = readl(&mxc_ccm->cs2cdr);
 791         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 792                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 793         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 794               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 795         writel(reg, &mxc_ccm->cs2cdr);
 796
 797         reg = readl(&mxc_ccm->cscmr2);
 798         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 799         writel(reg, &mxc_ccm->cscmr2);
 800
 801         reg = readl(&mxc_ccm->chsccdr);
 802         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 803                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 804         writel(reg, &mxc_ccm->chsccdr);
 805
 806         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 807              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 808              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 809              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 810              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 811              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 812              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 813              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 814              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 815         writel(reg, &iomux->gpr[2]);
 816
 817         reg = readl(&iomux->gpr[3]);
 818         reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
 819                         |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 820             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 821                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 822         writel(reg, &iomux->gpr[3]);
 823
 824         /* backlights off until needed */
 825         SETUP_IOMUX_PADS(backlight_pads);
 826         gpio_direction_input(LVDS_BACKLIGHT_GP);
 827         gpio_direction_input(RGB_BACKLIGHT_GP);
 828 }
 829 #endif
 830
 831 static iomux_v3_cfg_t const init_pads[] = {
 832         /* SGTL5000 sys_mclk */
 833         IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
 834
 835         /* J5 - Camera MCLK */
 836         IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
 837
 838         /* wl1271 pads on nitrogen6x */
 839         /* WL12XX_WL_IRQ_GP */
 840         IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
 841         /* WL12XX_WL_ENABLE_GP */
 842         IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
 843         /* WL12XX_BT_ENABLE_GP */
 844         IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
 845         /* USB otg power */
 846         IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
 847         IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
 848         IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
 849         IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
 850         IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
 851 };
 852
 853 #define WL12XX_WL_IRQ_GP        IMX_GPIO_NR(6, 14)
 854
 855 static unsigned gpios_out_low[] = {
 856         /* Disable wl1271 */
 857         IMX_GPIO_NR(6, 15),     /* disable wireless */
 858         IMX_GPIO_NR(6, 16),     /* disable bluetooth */
 859         IMX_GPIO_NR(3, 22),     /* disable USB otg power */
 860         IMX_GPIO_NR(2, 5),      /* ov5640 mipi camera reset */
 861         IMX_GPIO_NR(1, 8),      /* ov5642 reset */
 862 };
 863
 864 static unsigned gpios_out_high[] = {
 865         IMX_GPIO_NR(1, 6),      /* ov5642 powerdown */
 866         IMX_GPIO_NR(6, 9),      /* ov5640 mipi camera power down */
 867 };
 868
 869 static void set_gpios(unsigned *p, int cnt, int val)
 870 {
 871         int i;
 872
 873         for (i = 0; i < cnt; i++)
 874                 gpio_direction_output(*p++, val);
 875 }
 876
 877 int board_early_init_f(void)
 878 {
 879         setup_iomux_uart();
 880
 881         set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
 882         set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
 883         gpio_direction_input(WL12XX_WL_IRQ_GP);
 884
 885         SETUP_IOMUX_PADS(wl12xx_pads);
 886         SETUP_IOMUX_PADS(init_pads);
 887         setup_buttons();
 888
 889 #if defined(CONFIG_VIDEO_IPUV3)
 890         setup_display();
 891 #endif
 892         return 0;
 893 }
 894
 895 /*
 896  * Do not overwrite the console
 897  * Use always serial for U-Boot console
 898  */
 899 int overwrite_console(void)
 900 {
 901         return 1;
 902 }
 903
 904 int board_init(void)
 905 {
 906         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 907         struct i2c_pads_info *p = i2c_pads;
 908         int i;
 909         int stride = 1;
 910
 911 #if defined(CONFIG_MX6QDL)
 912         stride = 2;
 913         if (!is_mx6dq() && !is_mx6dqp())
 914                 p += 1;
 915 #endif
 916         clrsetbits_le32(&iomuxc_regs->gpr[1],
 917                         IOMUXC_GPR1_OTG_ID_MASK,
 918                         IOMUXC_GPR1_OTG_ID_GPIO1);
 919
 920         SETUP_IOMUX_PADS(misc_pads);
 921
 922         /* address of boot parameters */
 923         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 924
 925 #ifdef CONFIG_MXC_SPI
 926         setup_spi();
 927 #endif
 928         SETUP_IOMUX_PADS(usdhc2_pads);
 929         for (i = 0; i < I2C_BUS_CNT; i++) {
 930                 setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, p);
 931                 p += stride;
 932         }
 933
 934 #ifdef CONFIG_SATA
 935         setup_sata();
 936 #endif
 937
 938         return 0;
 939 }
 940
 941 int checkboard(void)
 942 {
 943         int ret = gpio_get_value(WL12XX_WL_IRQ_GP);
 944
 945         if (ret < 0) {
 946                 /* The gpios have not been probed yet. Read it myself */
 947                 struct gpio_regs *regs = (struct gpio_regs *)GPIO6_BASE_ADDR;
 948                 int gpio = WL12XX_WL_IRQ_GP & 0x1f;
 949
 950                 ret = (readl(&regs->gpio_psr) >> gpio) & 0x01;
 951         }
 952         if (ret)
 953                 puts("Board: Nitrogen6X\n");
 954         else
 955                 puts("Board: SABRE Lite\n");
 956
 957         return 0;
 958 }
 959
 960 struct button_key {
 961         char const      *name;
 962         unsigned        gpnum;
 963         char            ident;
 964 };
 965
 966 static struct button_key const buttons[] = {
 967         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 968         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 969         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 970         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 971         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 972         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 973 };
 974
 975 /*
 976  * generate a null-terminated string containing the buttons pressed
 977  * returns number of keys pressed
 978  */
 979 static int read_keys(char *buf)
 980 {
 981         int i, numpressed = 0;
 982         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 983                 if (!gpio_get_value(buttons[i].gpnum))
 984                         buf[numpressed++] = buttons[i].ident;
 985         }
 986         buf[numpressed] = '\0';
 987         return numpressed;
 988 }
 989
 990 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 991 {
 992         char envvalue[ARRAY_SIZE(buttons)+1];
 993         int numpressed = read_keys(envvalue);
 994         env_set("keybd", envvalue);
 995         return numpressed == 0;
 996 }
 997
 998 U_BOOT_CMD(
 999         kbd, 1, 1, do_kbd,
1000         "Tests for keypresses, sets 'keybd' environment variable",
1001         "Returns 0 (true) to shell if key is pressed."
1002 );
1003
1004 #ifdef CONFIG_PREBOOT
1005 static char const kbd_magic_prefix[] = "key_magic";
1006 static char const kbd_command_prefix[] = "key_cmd";
1007
1008 static void preboot_keys(void)
1009 {
1010         int numpressed;
1011         char keypress[ARRAY_SIZE(buttons)+1];
1012         numpressed = read_keys(keypress);
1013         if (numpressed) {
1014                 char *kbd_magic_keys = env_get("magic_keys");
1015                 char *suffix;
1016                 /*
1017                  * loop over all magic keys
1018                  */
1019                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
1020                         char *keys;
1021                         char magic[sizeof(kbd_magic_prefix) + 1];
1022                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
1023                         keys = env_get(magic);
1024                         if (keys) {
1025                                 if (!strcmp(keys, keypress))
1026                                         break;
1027                         }
1028                 }
1029                 if (*suffix) {
1030                         char cmd_name[sizeof(kbd_command_prefix) + 1];
1031                         char *cmd;
1032                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
1033                         cmd = env_get(cmd_name);
1034                         if (cmd) {
1035                                 env_set("preboot", cmd);
1036                                 return;
1037                         }
1038                 }
1039         }
1040 }
1041 #endif
1042
1043 #ifdef CONFIG_CMD_BMODE
1044 static const struct boot_mode board_boot_modes[] = {
1045         /* 4 bit bus width */
1046         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
1047         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
1048         {NULL,          0},
1049 };
1050 #endif
1051
1052 int misc_init_r(void)
1053 {
1054         gpio_request(RGB_BACKLIGHT_GP, "lvds backlight");
1055         gpio_request(LVDS_BACKLIGHT_GP, "lvds backlight");
1056         gpio_request(GP_USB_OTG_PWR, "usbotg power");
1057         gpio_request(IMX_GPIO_NR(7, 12), "usbh1 hub reset");
1058         gpio_request(IMX_GPIO_NR(2, 2), "back");
1059         gpio_request(IMX_GPIO_NR(2, 4), "home");
1060         gpio_request(IMX_GPIO_NR(2, 1), "menu");
1061         gpio_request(IMX_GPIO_NR(2, 3), "search");
1062         gpio_request(IMX_GPIO_NR(7, 13), "volup");
1063         gpio_request(IMX_GPIO_NR(4, 5), "voldown");
1064 #ifdef CONFIG_PREBOOT
1065         preboot_keys();
1066 #endif
1067
1068 #ifdef CONFIG_CMD_BMODE
1069         add_board_boot_modes(board_boot_modes);
1070 #endif
1071         env_set_hex("reset_cause", get_imx_reset_cause());
1072         return 0;
1073 }