board/bosch/guardian/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Bosch Guardian
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
   9  */
  10
  11 #include <common.h>
  12 #include <cpsw.h>
  13 #include <dm.h>
  14 #include <environment.h>
  15 #include <environment.h>
  16 #include <errno.h>
  17 #include <i2c.h>
  18 #include <miiphy.h>
  19 #include <panel.h>
  20 #include <power/tps65217.h>
  21 #include <power/tps65910.h>
  22 #include <spl.h>
  23 #include <watchdog.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/cpu.h>
  26 #include <asm/arch/ddr_defs.h>
  27 #include <asm/arch/gpio.h>
  28 #include <asm/arch/hardware.h>
  29 #include <asm/arch/mem.h>
  30 #include <asm/arch/mmc_host_def.h>
  31 #include <asm/arch/omap.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <asm/emif.h>
  34 #include <asm/gpio.h>
  35 #include <asm/io.h>
  36 #include "board.h"
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42
  43 static const struct ddr_data ddr3_data = {
  44         .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  45         .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  46         .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  47         .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  48 };
  49
  50 static const struct cmd_control ddr3_cmd_ctrl_data = {
  51         .cmd0csratio = MT41K128M16JT125K_RATIO,
  52         .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  53
  54         .cmd1csratio = MT41K128M16JT125K_RATIO,
  55         .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  56
  57         .cmd2csratio = MT41K128M16JT125K_RATIO,
  58         .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  59 };
  60
  61 static struct emif_regs ddr3_emif_reg_data = {
  62         .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  63         .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  64         .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  65         .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  66         .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  67         .zq_config = MT41K128M16JT125K_ZQ_CFG,
  68         .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  69 };
  70
  71 #define OSC     (V_OSCK / 1000000)
  72 const struct dpll_params dpll_ddr = {
  73                 400, OSC - 1, 1, -1, -1, -1, -1};
  74
  75 void am33xx_spl_board_init(void)
  76 {
  77         int mpu_vdd;
  78         int usb_cur_lim;
  79
  80         /* Get the frequency */
  81         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  82
  83         if (i2c_probe(TPS65217_CHIP_PM))
  84                 return;
  85
  86         /*
  87          * Increase USB current limit to 1300mA or 1800mA and set
  88          * the MPU voltage controller as needed.
  89          */
  90         if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  91                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  92                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  93         } else {
  94                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  95                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  96         }
  97
  98         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  99                                TPS65217_POWER_PATH,
 100                                usb_cur_lim,
 101                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 102                 puts("tps65217_reg_write failure\n");
 103
 104         /* Set DCDC3 (CORE) voltage to 1.125V */
 105         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 106                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 107                 puts("tps65217_voltage_update failure\n");
 108                 return;
 109         }
 110
 111         /* Set CORE Frequencies to OPP100 */
 112         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 113
 114         /* Set DCDC2 (MPU) voltage */
 115         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 116                 puts("tps65217_voltage_update failure\n");
 117                 return;
 118         }
 119
 120         /*
 121          * Set LDO3 to 1.8V and LDO4 to 3.3V
 122          */
 123         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 124                                TPS65217_DEFLS1,
 125                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 126                                TPS65217_LDO_MASK))
 127                 puts("tps65217_reg_write failure\n");
 128
 129         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 130                                TPS65217_DEFLS2,
 131                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 132                                TPS65217_LDO_MASK))
 133                 puts("tps65217_reg_write failure\n");
 134
 135         /* Set MPU Frequency to what we detected now that voltages are set */
 136         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 137 }
 138
 139 const struct dpll_params *get_dpll_ddr_params(void)
 140 {
 141         enable_i2c0_pin_mux();
 142         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 143
 144         return &dpll_ddr;
 145 }
 146
 147 void set_uart_mux_conf(void)
 148 {
 149         enable_uart0_pin_mux();
 150 }
 151
 152 void set_mux_conf_regs(void)
 153 {
 154         enable_board_pin_mux();
 155 }
 156
 157 const struct ctrl_ioregs ioregs = {
 158         .cm0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 159         .cm1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 160         .cm2ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 161         .dt0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 162         .dt1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 163 };
 164
 165 void sdram_init(void)
 166 {
 167         config_ddr(400, &ioregs,
 168                    &ddr3_data,
 169                    &ddr3_cmd_ctrl_data,
 170                    &ddr3_emif_reg_data, 0);
 171 }
 172 #endif
 173
 174 int board_init(void)
 175 {
 176 #if defined(CONFIG_HW_WATCHDOG)
 177         hw_watchdog_init();
 178 #endif
 179
 180         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 181
 182 #ifdef CONFIG_NAND
 183         gpmc_init();
 184 #endif
 185         return 0;
 186 }