board/bosch/guardian/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Bosch Guardian
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
   9  */
  10
  11 #include <common.h>
  12 #include <cpsw.h>
  13 #include <dm.h>
  14 #include <env_internal.h>
  15 #include <errno.h>
  16 #include <i2c.h>
  17 #include <miiphy.h>
  18 #include <panel.h>
  19 #include <power/tps65217.h>
  20 #include <power/tps65910.h>
  21 #include <spl.h>
  22 #include <watchdog.h>
  23 #include <asm/arch/clock.h>
  24 #include <asm/arch/cpu.h>
  25 #include <asm/arch/ddr_defs.h>
  26 #include <asm/arch/gpio.h>
  27 #include <asm/arch/hardware.h>
  28 #include <asm/arch/mem.h>
  29 #include <asm/arch/mmc_host_def.h>
  30 #include <asm/arch/omap.h>
  31 #include <asm/arch/sys_proto.h>
  32 #include <asm/emif.h>
  33 #include <asm/gpio.h>
  34 #include <asm/io.h>
  35 #include "board.h"
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  40 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  41
  42 static const struct ddr_data ddr3_data = {
  43         .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  44         .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  45         .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  46         .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  47 };
  48
  49 static const struct cmd_control ddr3_cmd_ctrl_data = {
  50         .cmd0csratio = MT41K128M16JT125K_RATIO,
  51         .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  52
  53         .cmd1csratio = MT41K128M16JT125K_RATIO,
  54         .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  55
  56         .cmd2csratio = MT41K128M16JT125K_RATIO,
  57         .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  58 };
  59
  60 static struct emif_regs ddr3_emif_reg_data = {
  61         .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  62         .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  63         .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  64         .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  65         .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  66         .zq_config = MT41K128M16JT125K_ZQ_CFG,
  67         .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  68 };
  69
  70 #define OSC     (V_OSCK / 1000000)
  71 const struct dpll_params dpll_ddr = {
  72                 400, OSC - 1, 1, -1, -1, -1, -1};
  73
  74 void am33xx_spl_board_init(void)
  75 {
  76         int mpu_vdd;
  77         int usb_cur_lim;
  78
  79         /* Get the frequency */
  80         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  81
  82         if (i2c_probe(TPS65217_CHIP_PM))
  83                 return;
  84
  85         /*
  86          * Increase USB current limit to 1300mA or 1800mA and set
  87          * the MPU voltage controller as needed.
  88          */
  89         if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  90                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  91                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  92         } else {
  93                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  94                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  95         }
  96
  97         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  98                                TPS65217_POWER_PATH,
  99                                usb_cur_lim,
 100                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 101                 puts("tps65217_reg_write failure\n");
 102
 103         /* Set DCDC3 (CORE) voltage to 1.125V */
 104         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 105                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 106                 puts("tps65217_voltage_update failure\n");
 107                 return;
 108         }
 109
 110         /* Set CORE Frequencies to OPP100 */
 111         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 112
 113         /* Set DCDC2 (MPU) voltage */
 114         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 115                 puts("tps65217_voltage_update failure\n");
 116                 return;
 117         }
 118
 119         /*
 120          * Set LDO3 to 1.8V and LDO4 to 3.3V
 121          */
 122         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 123                                TPS65217_DEFLS1,
 124                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 125                                TPS65217_LDO_MASK))
 126                 puts("tps65217_reg_write failure\n");
 127
 128         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 129                                TPS65217_DEFLS2,
 130                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 131                                TPS65217_LDO_MASK))
 132                 puts("tps65217_reg_write failure\n");
 133
 134         /* Set MPU Frequency to what we detected now that voltages are set */
 135         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 136 }
 137
 138 const struct dpll_params *get_dpll_ddr_params(void)
 139 {
 140         enable_i2c0_pin_mux();
 141         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 142
 143         return &dpll_ddr;
 144 }
 145
 146 void set_uart_mux_conf(void)
 147 {
 148         enable_uart0_pin_mux();
 149 }
 150
 151 void set_mux_conf_regs(void)
 152 {
 153         enable_board_pin_mux();
 154 }
 155
 156 const struct ctrl_ioregs ioregs = {
 157         .cm0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 158         .cm1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 159         .cm2ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 160         .dt0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 161         .dt1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 162 };
 163
 164 void sdram_init(void)
 165 {
 166         config_ddr(400, &ioregs,
 167                    &ddr3_data,
 168                    &ddr3_cmd_ctrl_data,
 169                    &ddr3_emif_reg_data, 0);
 170 }
 171 #endif
 172
 173 int board_init(void)
 174 {
 175         save_omap_boot_params();
 176
 177 #if defined(CONFIG_HW_WATCHDOG)
 178         hw_watchdog_init();
 179 #endif
 180
 181         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 182
 183 #ifdef CONFIG_NAND
 184         gpmc_init();
 185 #endif
 186         return 0;
 187 }
 188
 189 #ifdef CONFIG_BOARD_LATE_INIT
 190 static void set_bootmode_env(void)
 191 {
 192         char *boot_device_name = NULL;
 193         char *boot_mode_gpio = "gpio@44e07000_14";
 194         int   ret;
 195         int   value;
 196
 197         struct gpio_desc boot_mode_desc;
 198
 199         switch (gd->arch.omap_boot_device) {
 200         case BOOT_DEVICE_NAND:
 201                 boot_device_name = "nand";
 202                 break;
 203         case BOOT_DEVICE_USBETH:
 204                 boot_device_name = "usbeth";
 205                 break;
 206         default:
 207                 break;
 208         }
 209
 210         if (boot_device_name)
 211                 env_set("boot_device", boot_device_name);
 212
 213         ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
 214         if (ret) {
 215                 printf("%s is not found\n", boot_mode_gpio);
 216                 goto err;
 217         }
 218
 219         ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
 220         if (ret && ret != -EBUSY) {
 221                 printf("requesting gpio: %s failed\n", boot_mode_gpio);
 222                 goto err;
 223         }
 224
 225         value = dm_gpio_get_value(&boot_mode_desc);
 226         value ? env_set("swi_status", "0") : env_set("swi_status", "1");
 227         return;
 228
 229 err:
 230         env_set("swi_status", "err");
 231 }
 232
 233 int board_late_init(void)
 234 {
 235         set_bootmode_env();
 236         return 0;
 237 }
 238 #endif /* CONFIG_BOARD_LATE_INIT */