board/bluewater/snapper9260/snapper9260.c

   1 /*
   2  * Bluewater Systems Snapper 9260/9G20 modules
   3  *
   4  * (C) Copyright 2011 Bluewater Systems
   5  *   Author: Andre Renaud <andre@bluewatersys.com>
   6  *   Author: Ryan Mallon <ryan@bluewatersys.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <dm.h>
  13 #include <asm/io.h>
  14 #include <asm/gpio.h>
  15 #include <asm/arch/at91sam9260_matrix.h>
  16 #include <asm/arch/at91sam9_smc.h>
  17 #include <asm/arch/at91_common.h>
  18 #include <asm/arch/at91_pmc.h>
  19 #include <asm/arch/gpio.h>
  20 #include <asm/arch/atmel_serial.h>
  21 #include <net.h>
  22 #include <netdev.h>
  23 #include <i2c.h>
  24 #include <pca953x.h>
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /* IO Expander pins */
  29 #define IO_EXP_ETH_RESET        (0 << 1)
  30 #define IO_EXP_ETH_POWER        (1 << 1)
  31
  32 static void macb_hw_init(void)
  33 {
  34         struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
  35         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  36
  37         /* Enable clock */
  38         writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  39
  40         /* Disable pull-ups to prevent PHY going into test mode */
  41         writel(pin_to_mask(AT91_PIN_PA14) |
  42                pin_to_mask(AT91_PIN_PA15) |
  43                pin_to_mask(AT91_PIN_PA18),
  44                &pioa->pudr);
  45
  46         /* Power down ethernet */
  47         pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
  48         pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
  49
  50         /* Hold ethernet in reset */
  51         pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
  52         pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
  53
  54         /* Enable ethernet power */
  55         pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
  56
  57         at91_phy_reset();
  58
  59         /* Bring the ethernet out of reset */
  60         pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
  61
  62         /* The phy internal reset take 21ms */
  63         udelay(21 * 1000);
  64
  65         /* Re-enable pull-up */
  66         writel(pin_to_mask(AT91_PIN_PA14) |
  67                pin_to_mask(AT91_PIN_PA15) |
  68                pin_to_mask(AT91_PIN_PA18),
  69                &pioa->puer);
  70
  71         at91_macb_hw_init();
  72 }
  73
  74 static void nand_hw_init(void)
  75 {
  76         struct at91_smc *smc       = (struct at91_smc    *)ATMEL_BASE_SMC;
  77         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  78         unsigned long csa;
  79
  80         /* Enable CS3 as NAND/SmartMedia */
  81         csa = readl(&matrix->ebicsa);
  82         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  83         writel(csa, &matrix->ebicsa);
  84
  85         /* Configure SMC CS3 for NAND/SmartMedia */
  86         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
  87                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  88                &smc->cs[3].setup);
  89         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
  90                AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
  91                &smc->cs[3].pulse);
  92         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
  93                &smc->cs[3].cycle);
  94         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  95                AT91_SMC_MODE_EXNW_DISABLE |
  96                AT91_SMC_MODE_DBW_8 |
  97                AT91_SMC_MODE_TDF_CYCLE(3),
  98                &smc->cs[3].mode);
  99
 100         /* Configure RDY/BSY */
 101         gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
 102         gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 103
 104         /* Enable NandFlash */
 105         gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
 106         gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 107 }
 108
 109 int board_init(void)
 110 {
 111         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 112
 113         /* Enable PIO clocks */
 114         writel((1 << ATMEL_ID_PIOA) |
 115                (1 << ATMEL_ID_PIOB) |
 116                (1 << ATMEL_ID_PIOC), &pmc->pcer);
 117
 118         /* The mach-type is the same for both Snapper 9260 and 9G20 */
 119         gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
 120
 121         /* Address of boot parameters */
 122         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 123
 124         /* Initialise peripherals */
 125         at91_seriald_hw_init();
 126         i2c_set_bus_num(0);
 127         nand_hw_init();
 128         macb_hw_init();
 129
 130         return 0;
 131 }
 132
 133 int board_eth_init(bd_t *bis)
 134 {
 135         return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
 136 }
 137
 138 int dram_init(void)
 139 {
 140         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 141                                     CONFIG_SYS_SDRAM_SIZE);
 142         return 0;
 143 }
 144
 145 void reset_phy(void)
 146 {
 147 }
 148
 149 static struct atmel_serial_platdata at91sam9260_serial_plat = {
 150         .base_addr = ATMEL_BASE_DBGU,
 151 };
 152
 153 U_BOOT_DEVICE(at91sam9260_serial) = {
 154         .name   = "serial_atmel",
 155         .platdata = &at91sam9260_serial_plat,
 156 };