9 #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
10 #define CLKIN 25000000
11 #define PATTERN1 0x5A5A5A5A
12 #define PATTERN2 0xAAAAAAAA
17 void post_out_buff(char *buff);
18 int post_key_pressed(void);
19 void post_init_pll(int mult, int div);
20 int post_init_sdram(int sclk);
21 void post_init_uart(int sclk);
23 const int pll[CCLK_NUM][SCLK_NUM][2] = {
24 { {20, 4}, {20, 5}, {20, 10} }, /* CCLK = 500M */
25 { {16, 4}, {16, 5}, {16, 8} }, /* CCLK = 400M */
26 { {8, 2}, {8, 4}, {8, 5} }, /* CCLK = 200M */
27 { {4, 1}, {4, 2}, {4, 4} } /* CCLK = 100M */
29 const char *const log[CCLK_NUM][SCLK_NUM] = {
30 {"CCLK-500MHz SCLK-125MHz: Writing...\0",
31 "CCLK-500MHz SCLK-100MHz: Writing...\0",
32 "CCLK-500MHz SCLK- 50MHz: Writing...\0",},
33 {"CCLK-400MHz SCLK-100MHz: Writing...\0",
34 "CCLK-400MHz SCLK- 80MHz: Writing...\0",
35 "CCLK-400MHz SCLK- 50MHz: Writing...\0",},
36 {"CCLK-200MHz SCLK-100MHz: Writing...\0",
37 "CCLK-200MHz SCLK- 50MHz: Writing...\0",
38 "CCLK-200MHz SCLK- 40MHz: Writing...\0",},
39 {"CCLK-100MHz SCLK-100MHz: Writing...\0",
40 "CCLK-100MHz SCLK- 50MHz: Writing...\0",
41 "CCLK-100MHz SCLK- 25MHz: Writing...\0",},
44 int memory_post_test(int flags)
51 sclk_temp = CLKIN / 1000000;
52 sclk_temp = sclk_temp * CONFIG_VCO_MULT;
53 for (sclk = 0; sclk_temp > 0; sclk++)
54 sclk_temp -= CONFIG_SCLK_DIV;
55 sclk = sclk * 1000000;
57 if (post_key_pressed() == 0)
60 for (m = 0; m < CCLK_NUM; m++) {
61 for (n = 0; n < SCLK_NUM; n++) {
62 /* Calculate the sclk */
63 sclk_temp = CLKIN / 1000000;
64 sclk_temp = sclk_temp * pll[m][n][0];
65 for (sclk = 0; sclk_temp > 0; sclk++)
66 sclk_temp -= pll[m][n][1];
67 sclk = sclk * 1000000;
69 post_init_pll(pll[m][n][0], pll[m][n][1]);
70 post_init_sdram(sclk);
72 post_out_buff("\n\r\0");
73 post_out_buff(log[m][n]);
74 for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
75 *(unsigned long *)addr = PATTERN1;
76 post_out_buff("Reading...\0");
77 for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
78 if ((*(unsigned long *)addr) != PATTERN1) {
79 post_out_buff("Error\n\r\0");
83 post_out_buff("OK\n\r\0");
87 post_out_buff("memory POST passed\n\r\0");
89 post_out_buff("memory POST failed\n\r\0");
91 post_out_buff("\n\r\n\r\0");
95 void post_init_uart(int sclk)
99 for (divisor = 0; sclk > 0; divisor++)
102 *pPORTF_FER = 0x000F;
103 *pPORTH_FER = 0xFFFF;
108 *pUART_DLL = (divisor & 0xFF);
110 *pUART_DLH = ((divisor >> 8) & 0xFF);
118 void post_out_buff(char *buff)
122 for (i = 0; i < 0x80000; i++)
125 while ((buff[i] != '\0') && (i != 100)) {
126 while (!(*pUART_LSR & 0x20)) ;
127 *pUART_THR = buff[i];
131 for (i = 0; i < 0x80000; i++)
135 /* Using sw10-PF5 as the hotkey */
136 #define KEY_LOOP 0x80000
137 #define KEY_DELAY 0x80
138 int post_key_pressed(void)
141 unsigned short value;
144 *pPORTFIO_DIR &= ~PF5;
145 *pPORTFIO_INEN |= PF5;
148 post_out_buff("########Press SW10 to enter Memory POST########: 3\0");
149 for (i = 0; i < KEY_LOOP; i++) {
150 value = *pPORTFIO & PF5;
151 if (*pUART0_RBR == 0x0D) {
157 for (n = 0; n < KEY_DELAY; n++)
160 post_out_buff("\b2\0");
162 for (i = 0; i < KEY_LOOP; i++) {
163 value = *pPORTFIO & PF5;
164 if (*pUART0_RBR == 0x0D) {
170 for (n = 0; n < KEY_DELAY; n++)
173 post_out_buff("\b1\0");
175 for (i = 0; i < KEY_LOOP; i++) {
176 value = *pPORTFIO & PF5;
177 if (*pUART0_RBR == 0x0D) {
183 for (n = 0; n < KEY_DELAY; n++)
187 post_out_buff("\b0");
188 post_out_buff("\n\r\0");
191 post_out_buff("Hotkey has been pressed, Enter POST . . . . . .\n\r\0");
195 void post_init_pll(int mult, int div)
199 *pPLL_CTL = (mult << 9);
204 while (!(*pPLL_STAT & 0x20)) ;
207 int post_init_sdram(int sclk)
209 int SDRAM_tRP, SDRAM_tRP_num, SDRAM_tRAS, SDRAM_tRAS_num, SDRAM_tRCD,
211 int SDRAM_Tref, SDRAM_NRA, SDRAM_CL, SDRAM_SIZE, SDRAM_WIDTH,
212 mem_SDGCTL, mem_SDBCTL, mem_SDRRC;
214 if ((sclk > 119402985)) {
221 } else if ((sclk > 104477612) && (sclk <= 119402985)) {
228 } else if ((sclk > 89552239) && (sclk <= 104477612)) {
235 } else if ((sclk > 74626866) && (sclk <= 89552239)) {
242 } else if ((sclk > 66666667) && (sclk <= 74626866)) {
249 } else if ((sclk > 59701493) && (sclk <= 66666667)) {
256 } else if ((sclk > 44776119) && (sclk <= 59701493)) {
263 } else if ((sclk > 29850746) && (sclk <= 44776119)) {
270 } else if (sclk <= 29850746) {
285 /*SDRAM INFORMATION: */
286 SDRAM_Tref = 64; /* Refresh period in milliseconds */
287 SDRAM_NRA = 4096; /* Number of row addresses in SDRAM */
288 SDRAM_CL = CL_3; /* 2 */
290 SDRAM_SIZE = EBSZ_64;
291 SDRAM_WIDTH = EBCAW_10;
293 mem_SDBCTL = SDRAM_WIDTH | SDRAM_SIZE | EBE;
295 /* Equation from section 17 (p17-46) of BF533 HRM */
297 (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) -
298 (SDRAM_tRAS_num + SDRAM_tRP_num);
300 /* Enable SCLK Out */
302 (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR
307 *pEBIU_SDGCTL |= 0x1000000;
308 /* Set the SDRAM Refresh Rate control register based on SSCLK value */
309 *pEBIU_SDRRC = mem_SDRRC;
311 /* SDRAM Memory Bank Control Register */
312 *pEBIU_SDBCTL = mem_SDBCTL;
314 /* SDRAM Memory Global Control Register */
315 *pEBIU_SDGCTL = mem_SDGCTL;
320 #endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
321 #endif /* CONFIG_POST */