2 * video.c - run splash screen on lcd
4 * Copyright (c) 2007-2008 Analog Devices Inc.
6 * Licensed under the GPL-2 or later.
13 #include <asm/blackfin.h>
14 #include <asm/portmux.h>
15 #include <asm/mach-common/bits/dma.h>
17 #include <linux/types.h>
18 #include <stdio_dev.h>
20 #include <asm/mach-common/bits/ppi.h>
21 #include <asm/mach-common/bits/timer.h>
23 #define LCD_X_RES 320 /* Horizontal Resolution */
24 #define LCD_Y_RES 240 /* Vertical Resolution */
25 #define DMA_BUS_SIZE 16
27 #ifdef CONFIG_BF527_EZKIT_REV_2_1 /* lq035q1 */
29 #if !defined(CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI) && \
30 !defined(CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI)
31 # define CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
34 /* Interface 16/18-bit TFT over an 8-bit wide PPI using a
35 * small Programmable Logic Device (CPLD)
36 * http://blackfin.uclinux.org/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_id=165
39 #ifdef CONFIG_LQ035Q1_USE_RGB565_8_BIT_PPI
40 #include <asm/bfin_logo_rgb565_230x230.h>
41 #define LCD_BPP 16 /* Bit Per Pixel */
42 #define CLOCKS_PPIX 2 /* Clocks per pixel */
43 #define CPLD_DELAY 3 /* RGB565 pipeline delay */
46 #ifdef CONFIG_LQ035Q1_USE_RGB888_8_BIT_PPI
47 #include <asm/bfin_logo_230x230.h>
48 #define LCD_BPP 24 /* Bit Per Pixel */
49 #define CLOCKS_PPIX 3 /* Clocks per pixel */
50 #define CPLD_DELAY 5 /* RGB888 pipeline delay */
54 * HS and VS timing parameters (all in number of PPI clk ticks)
57 #define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
58 #define H_PERIOD (336 * CLOCKS_PPIX) /* HS period */
59 #define H_PULSE (2 * CLOCKS_PPIX) /* HS pulse width */
60 #define H_START (7 * CLOCKS_PPIX + CPLD_DELAY) /* first valid pixel */
62 #define U_LINE 4 /* Blanking Lines */
64 #define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
65 #define V_PULSE (2 * CLOCKS_PPIX) /* VS pulse width (1-5 H_PERIODs) */
66 #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
68 #define ACTIVE_VIDEO_MEM_OFFSET ((U_LINE / 2) * LCD_X_RES * (LCD_BPP / 8))
73 #define LQ035_RL (0 << 8) /* Right -> Left Scan */
74 #define LQ035_LR (1 << 8) /* Left -> Right Scan */
75 #define LQ035_TB (1 << 9) /* Top -> Botton Scan */
76 #define LQ035_BT (0 << 9) /* Botton -> Top Scan */
77 #define LQ035_BGR (1 << 11) /* Use BGR format */
78 #define LQ035_RGB (0 << 11) /* Use RGB format */
79 #define LQ035_NORM (1 << 13) /* Reversal */
80 #define LQ035_REV (0 << 13) /* Reversal */
82 #define LQ035_INDEX 0x74
83 #define LQ035_DATA 0x76
85 #define LQ035_DRIVER_OUTPUT_CTL 0x1
86 #define LQ035_SHUT_CTL 0x11
88 #define LQ035_DRIVER_OUTPUT_MASK (LQ035_LR | LQ035_TB | LQ035_BGR | LQ035_REV)
89 #define LQ035_DRIVER_OUTPUT_DEFAULT (0x2AEF & ~LQ035_DRIVER_OUTPUT_MASK)
91 #define LQ035_SHUT (1 << 0) /* Shutdown */
92 #define LQ035_ON (0 << 0) /* Shutdown */
94 #ifndef CONFIG_LQ035Q1_LCD_MODE
95 #define CONFIG_LQ035Q1_LCD_MODE (LQ035_NORM | LQ035_RL | LQ035_TB | LQ035_BGR)
99 #include <asm/bfin_logo_230x230.h>
101 #define LCD_BPP 24 /* Bit Per Pixel */
102 #define CLOCKS_PPIX 3 /* Clocks per pixel */
104 /* HS and VS timing parameters (all in number of PPI clk ticks) */
105 #define H_ACTPIX (LCD_X_RES * CLOCKS_PPIX) /* active horizontal pixel */
106 #define H_PERIOD (408 * CLOCKS_PPIX) /* HS period */
107 #define H_PULSE 90 /* HS pulse width */
108 #define H_START 204 /* first valid pixel */
110 #define U_LINE 1 /* Blanking Lines */
112 #define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */
113 #define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */
114 #define V_PERIOD (H_PERIOD * V_LINES) /* VS period */
116 #define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX)
119 #define LCD_PIXEL_SIZE (LCD_BPP / 8)
122 #define PPI_TX_MODE 0x2
123 #define PPI_XFER_TYPE_11 0xC
124 #define PPI_PORT_CFG_01 0x10
125 #define PPI_PACK_EN 0x80
126 #define PPI_POLS_1 0x8000
128 #ifdef CONFIG_BF527_EZKIT_REV_2_1
129 static struct spi_slave *slave;
130 static int lq035q1_control(unsigned char reg, unsigned short value)
133 u8 regs[3] = {LQ035_INDEX, 0, 0};
134 u8 data[3] = {LQ035_DATA, 0, 0};
138 data[1] = value >> 8;
139 data[2] = value & 0xFF;
142 /* FIXME: Verify the max SCK rate */
143 slave = spi_setup_slave(CONFIG_LQ035Q1_SPI_BUS,
144 CONFIG_LQ035Q1_SPI_CS, 20000000,
150 if (spi_claim_bus(slave))
153 ret = spi_xfer(slave, 24, regs, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
154 ret |= spi_xfer(slave, 24, data, dummy, SPI_XFER_BEGIN | SPI_XFER_END);
156 spi_release_bus(slave);
162 /* enable and disable PPI functions */
165 bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() | PORT_EN);
168 void DisablePPI(void)
170 bfin_write_PPI_CONTROL(bfin_read_PPI_CONTROL() & ~PORT_EN);
173 void Init_Ports(void)
175 const unsigned short pins[] = {
176 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
177 P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
179 peripheral_request_list(pins, "lcd");
185 bfin_write_PPI_DELAY(H_START);
186 bfin_write_PPI_COUNT(H_ACTPIX - 1);
187 bfin_write_PPI_FRAME(V_LINES);
189 /* PPI control, to be replaced with definitions */
190 bfin_write_PPI_CONTROL(
191 PPI_TX_MODE | /* output mode , PORT_DIR */
192 PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */
193 PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */
194 PPI_PACK_EN | /* packing enabled PACK_EN */
195 PPI_POLS_1 /* faling edge syncs POLS */
199 void Init_DMA(void *dst)
201 bfin_write_DMA0_START_ADDR(dst);
204 bfin_write_DMA0_X_COUNT(H_ACTPIX / 2);
205 bfin_write_DMA0_X_MODIFY(DMA_BUS_SIZE / 8);
208 bfin_write_DMA0_Y_COUNT(V_LINES);
209 bfin_write_DMA0_Y_MODIFY(DMA_BUS_SIZE / 8);
212 bfin_write_DMA0_CONFIG(
213 WDSIZE_16 | /* 16 bit DMA */
215 FLOW_AUTO /* autobuffer mode */
221 bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() | DMAEN);
224 void DisableDMA(void)
226 bfin_write_DMA0_CONFIG(bfin_read_DMA0_CONFIG() & ~DMAEN);
229 /* Init TIMER0 as Frame Sync 1 generator */
230 void InitTIMER0(void)
232 bfin_write_TIMER_DISABLE(TIMDIS0); /* disable Timer */
234 bfin_write_TIMER_STATUS(TIMIL0 | TOVF_ERR0 | TRUN0); /* clear status */
237 bfin_write_TIMER0_PERIOD(H_PERIOD);
239 bfin_write_TIMER0_WIDTH(H_PULSE);
242 bfin_write_TIMER0_CONFIG(
252 void EnableTIMER0(void)
254 bfin_write_TIMER_ENABLE(TIMEN0);
258 void DisableTIMER0(void)
260 bfin_write_TIMER_DISABLE(TIMDIS0);
265 void InitTIMER1(void)
267 bfin_write_TIMER_DISABLE(TIMDIS1); /* disable Timer */
269 bfin_write_TIMER_STATUS(TIMIL1 | TOVF_ERR1 | TRUN1); /* clear status */
272 bfin_write_TIMER1_PERIOD(V_PERIOD);
274 bfin_write_TIMER1_WIDTH(V_PULSE);
277 bfin_write_TIMER1_CONFIG(
287 void EnableTIMER1(void)
289 bfin_write_TIMER_ENABLE(TIMEN1);
293 void DisableTIMER1(void)
295 bfin_write_TIMER_DISABLE(TIMDIS1);
299 void EnableTIMER12(void)
301 bfin_write_TIMER_ENABLE(TIMEN1 | TIMEN0);
305 int video_init(void *dst)
308 #ifdef CONFIG_BF527_EZKIT_REV_2_1
309 lq035q1_control(LQ035_SHUT_CTL, LQ035_ON);
310 lq035q1_control(LQ035_DRIVER_OUTPUT_CTL, (CONFIG_LQ035Q1_LCD_MODE &
311 LQ035_DRIVER_OUTPUT_MASK) | LQ035_DRIVER_OUTPUT_DEFAULT);
321 #ifdef CONFIG_BF527_EZKIT_REV_2_1
324 /* Frame sync 2 (VS) needs to start at least one PPI clk earlier */
326 /* Add Some Delay ... */
332 /* now start frame sync 1 */
339 static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
342 blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
344 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
346 /* Setup destination start address */
347 bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
348 + (y * LCD_X_RES * LCD_PIXEL_SIZE));
349 /* Setup destination xcount */
350 bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
351 /* Setup destination xmodify */
352 bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
354 /* Setup destination ycount */
355 bfin_write_MDMA_D0_Y_COUNT(logo->height);
356 /* Setup destination ymodify */
357 bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
360 /* Setup Source start address */
361 bfin_write_MDMA_S0_START_ADDR(logo->data);
362 /* Setup Source xcount */
363 bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
364 /* Setup Source xmodify */
365 bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
367 /* Setup Source ycount */
368 bfin_write_MDMA_S0_Y_COUNT(logo->height);
369 /* Setup Source ymodify */
370 bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
373 /* Enable source DMA */
374 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
376 bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
378 while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
380 bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
381 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
385 void video_stop(void)
391 #ifdef CONFIG_BF527_EZKIT_REV_2_1
392 lq035q1_control(LQ035_SHUT_CTL, LQ035_SHUT);
396 void video_putc(const char c)
400 void video_puts(const char *s)
404 int drv_video_init(void)
406 int error, devices = 1;
407 struct stdio_dev videodev;
410 u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
412 dst = malloc(fbmem_size);
415 printf("Failed to alloc FB memory\n");
419 #ifdef EASYLOGO_ENABLE_GZIP
420 unsigned char *data = EASYLOGO_DECOMP_BUFFER;
421 unsigned long src_len = EASYLOGO_ENABLE_GZIP;
422 if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) {
423 puts("Failed to decompress logo\n");
427 bfin_logo.data = data;
430 memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
432 dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
433 (LCD_X_RES - bfin_logo.width) / 2,
434 (LCD_Y_RES - bfin_logo.height) / 2);
436 video_init(dst); /* Video initialization */
438 memset(&videodev, 0, sizeof(videodev));
440 strcpy(videodev.name, "video");
441 videodev.ext = DEV_EXT_VIDEO; /* Video extensions */
442 videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */
443 videodev.putc = video_putc; /* 'putc' function */
444 videodev.puts = video_puts; /* 'puts' function */
446 error = stdio_register(&videodev);
448 return (error == 0) ? devices : error;