2 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
3 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 * Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
6 * Copyright (C) 2011 Freescale Semiconductor, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/sys_proto.h>
15 #include <asm/arch/crm_regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/iomux-mx53.h>
18 #include <asm/arch/clock.h>
19 #include <asm/imx-common/mx5_video.h>
24 #include <fsl_esdhc.h>
27 #include <ipu_pixfmt.h>
29 #include <dm/platdata.h>
30 #include <dm/platform_data/serial_mxc.h>
33 GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
34 GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
35 GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
36 GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
37 GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
38 GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
39 GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
40 GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
41 GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
42 GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
43 GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
44 GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
45 GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
46 GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
47 GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
50 #define CCAT_BASE_ADDR ((void *)0xf0000000)
51 #define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
52 #define CCAT_SIZE 1191788
53 #define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
54 static const char CCAT_SIGNATURE[] = "CCAT";
56 static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
57 static const u32 CCAT_MODE_RUN = 0x0033DC8F;
59 DECLARE_GLOBAL_DATA_PTR;
61 static uint32_t mx53_dram_size[2];
63 phys_size_t get_effective_memsize(void)
66 * WARNING: We must override get_effective_memsize() function here
67 * to report only the size of the first DRAM bank. This is to make
68 * U-Boot relocator place U-Boot into valid memory, that is, at the
69 * end of the first DRAM bank. If we did not override this function
70 * like so, U-Boot would be placed at the address of the first DRAM
71 * bank + total DRAM size - sizeof(uboot), which in the setup where
72 * each DRAM bank contains 512MiB of DRAM would result in placing
73 * U-Boot into invalid memory area close to the end of the first
76 return mx53_dram_size[0];
81 mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
82 mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
84 gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
89 void dram_init_banksize(void)
91 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
92 gd->bd->bi_dram[0].size = mx53_dram_size[0];
94 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
95 gd->bd->bi_dram[1].size = mx53_dram_size[1];
98 u32 get_board_rev(void)
100 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
101 struct fuse_bank *bank = &iim->bank[0];
102 struct fuse_bank0_regs *fuse =
103 (struct fuse_bank0_regs *)bank->fuse_regs;
105 int rev = readl(&fuse->gp[6]);
107 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
112 * @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
114 void weim_cs0_settings(u32 mode)
116 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
118 writel(0x0, &weim_regs->cs0gcr1);
119 writel(mode, &weim_regs->cs0gcr1);
120 writel(0x00001002, &weim_regs->cs0gcr2);
122 writel(0x04000000, &weim_regs->cs0rcr1);
123 writel(0x00000000, &weim_regs->cs0rcr2);
125 writel(0x04000000, &weim_regs->cs0wcr1);
126 writel(0x00000000, &weim_regs->cs0wcr2);
129 static void setup_gpio_eim(void)
131 gpio_direction_input(GPIO_C3_STATUS);
132 gpio_direction_input(GPIO_C3_DONE);
133 gpio_direction_output(GPIO_C3_CONFIG, 1);
135 weim_cs0_settings(CCAT_MODE_RUN);
138 static void setup_gpio_sups(void)
140 gpio_direction_input(GPIO_SUPS_INT);
142 static const int BLINK_INTERVALL = 50000;
144 while (gpio_get_value(GPIO_SUPS_INT)) {
145 /* signal "CX SUPS power fail" */
146 gpio_set_value(GPIO_LED_PWR_R,
147 (++status / BLINK_INTERVALL) % 2);
150 /* signal "CX power up" */
151 gpio_set_value(GPIO_LED_PWR_R, 1);
154 static void setup_gpio_leds(void)
156 gpio_direction_output(GPIO_LED_SD2_R, 0);
157 gpio_direction_output(GPIO_LED_SD2_B, 0);
158 gpio_direction_output(GPIO_LED_SD2_G, 0);
159 gpio_direction_output(GPIO_LED_SD1_R, 0);
160 gpio_direction_output(GPIO_LED_SD1_B, 0);
161 gpio_direction_output(GPIO_LED_SD1_G, 0);
162 gpio_direction_output(GPIO_LED_PWR_R, 0);
163 gpio_direction_output(GPIO_LED_PWR_B, 0);
164 gpio_direction_output(GPIO_LED_PWR_G, 0);
167 #ifdef CONFIG_USB_EHCI_MX5
168 int board_ehci_hcd_init(int port)
170 /* request VBUS power enable pin, GPIO7_8 */
171 gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
176 #ifdef CONFIG_FSL_ESDHC
177 struct fsl_esdhc_cfg esdhc_cfg[2] = {
178 {MMC_SDHC1_BASE_ADDR},
179 {MMC_SDHC2_BASE_ADDR},
182 int board_mmc_getcd(struct mmc *mmc)
184 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
187 gpio_direction_input(GPIO_SD1_CD);
188 gpio_direction_input(GPIO_SD2_CD);
190 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
191 ret = !gpio_get_value(GPIO_SD1_CD);
193 ret = !gpio_get_value(GPIO_SD2_CD);
198 int board_mmc_init(bd_t *bis)
203 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
204 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
206 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
213 printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n",
214 CONFIG_SYS_FSL_ESDHC_NUM);
217 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
226 static int power_init(void)
228 /* nothing to do on CX9020 */
232 static void clock_1GHz(void)
235 u32 ref_clk = MXC_HCLK;
237 * After increasing voltage to 1.25V, we can switch
238 * CPU clock to 1GHz and DDR to 400MHz safely
240 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
242 printf("CPU: Switch CPU clock to 1GHZ failed\n");
244 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
245 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
247 printf("CPU: Switch DDR clock to 400MHz failed\n");
250 int board_early_init_f(void)
261 * Do not overwrite the console
262 * Use always serial for U-Boot console
264 int overwrite_console(void)
271 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
273 mxc_set_sata_internal_clock();
280 puts("Board: Beckhoff CX9020\n");
285 static int ccat_config_fn(int assert_config, int flush, int cookie)
287 /* prepare FPGA for programming */
288 weim_cs0_settings(CCAT_MODE_CONFIG);
289 gpio_set_value(GPIO_C3_CONFIG, 0);
291 gpio_set_value(GPIO_C3_CONFIG, 1);
297 static int ccat_status_fn(int cookie)
302 static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
304 const uint8_t *const buffer = buf;
308 for (i = 0; i < buf_len; ++i)
309 writeb(buffer[i], CCAT_BASE_ADDR);
311 writeb(0xff, CCAT_BASE_ADDR);
312 writeb(0xff, CCAT_BASE_ADDR);
317 static int ccat_done_fn(int cookie)
319 /* programming complete? */
320 return gpio_get_value(GPIO_C3_DONE);
323 static int ccat_post_fn(int cookie)
325 /* switch to FPGA run mode */
326 weim_cs0_settings(CCAT_MODE_RUN);
327 invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
329 if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
330 printf("Verifing CCAT firmware failed, signature not found\n");
334 /* signal "CX booting OS" */
335 gpio_set_value(GPIO_LED_PWR_R, 1);
336 gpio_set_value(GPIO_LED_PWR_G, 1);
337 gpio_set_value(GPIO_LED_PWR_B, 0);
341 static Altera_CYC2_Passive_Serial_fns ccat_fns = {
342 .config = ccat_config_fn,
343 .status = ccat_status_fn,
344 .done = ccat_done_fn,
345 .write = ccat_write_fn,
346 .abort = ccat_post_fn,
347 .post = ccat_post_fn,
350 static Altera_desc ccat_fpga = {
351 .family = Altera_CYC2,
352 .iface = passive_serial,
354 .iface_fns = &ccat_fns,
355 .base = CCAT_BASE_ADDR,
358 int board_late_init(void)
364 fpga_add(fpga_altera, &ccat_fpga);