4 * (C) Copyright 2003-2004
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
10 * (C) Copyright 2004-2005
11 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
14 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de
17 * 1.1 - improved SM501 init to meet spec timing
19 * See file CREDITS for list of people who contributed to this
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 #ifdef CONFIG_VIDEO_SM501
46 #if defined(CONFIG_MPC5200_DDR)
47 #include "mt46v16m16-75.h"
49 #include "mt48lc16m16a2-75.h"
52 #ifdef CONFIG_RTC_MPC5200
57 void ps2mult_early_init(void);
61 static void sdram_start (int hi_addr)
63 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
65 /* unlock mode register */
66 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
68 __asm__ volatile ("sync");
70 /* precharge all banks */
71 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
73 __asm__ volatile ("sync");
76 /* set mode register: extended mode */
77 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
78 __asm__ volatile ("sync");
80 /* set mode register: reset DLL */
81 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
82 __asm__ volatile ("sync");
85 /* precharge all banks */
86 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
88 __asm__ volatile ("sync");
91 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
93 __asm__ volatile ("sync");
95 /* set mode register */
96 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
97 __asm__ volatile ("sync");
99 /* normal operation */
100 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
101 __asm__ volatile ("sync");
106 * ATTENTION: Although partially referenced initdram does NOT make real use
107 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
108 * is something else than 0x00000000.
111 #if defined(CONFIG_MPC5200)
112 long int initdram (int board_type)
119 /* setup SDRAM chip selects */
120 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
121 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
122 __asm__ volatile ("sync");
124 /* setup config registers */
125 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
126 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
127 __asm__ volatile ("sync");
131 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
132 __asm__ volatile ("sync");
135 /* find RAM size using SDRAM CS0 only */
137 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
139 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
147 /* memory smaller than 1MB is impossible */
148 if (dramsize < (1 << 20)) {
152 /* set SDRAM CS0 size according to the amount of RAM found */
154 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
155 __builtin_ffs(dramsize >> 20) - 1;
157 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
160 /* let SDRAM CS1 start right after CS0 */
161 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
163 /* find RAM size using SDRAM CS1 only */
165 test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
167 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
175 /* memory smaller than 1MB is impossible */
176 if (dramsize2 < (1 << 20)) {
180 /* set SDRAM CS1 size according to the amount of RAM found */
182 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
183 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
185 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
188 #else /* CFG_RAMBOOT */
190 /* retrieve size of memory connected to SDRAM CS0 */
191 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
192 if (dramsize >= 0x13) {
193 dramsize = (1 << (dramsize - 0x13)) << 20;
198 /* retrieve size of memory connected to SDRAM CS1 */
199 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
200 if (dramsize2 >= 0x13) {
201 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
206 #endif /* CFG_RAMBOOT */
211 #elif defined(CONFIG_MGT5100)
213 long int initdram (int board_type)
219 /* setup and enable SDRAM chip selects */
220 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
221 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff; /* 2G */
222 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
223 __asm__ volatile ("sync");
225 /* setup config registers */
226 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
227 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
229 /* address select register */
230 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
231 __asm__ volatile ("sync");
235 test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
237 test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
245 /* set SDRAM end address according to size */
246 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
248 #else /* CFG_RAMBOOT */
250 /* Retrieve amount of SDRAM available */
251 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
253 #endif /* CFG_RAMBOOT */
259 #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
262 int checkboard (void)
264 #if defined (CONFIG_TQM5200)
265 puts ("Board: TQM5200 (TQ-Components GmbH)\n");
268 #if defined (CONFIG_BC3450)
269 puts ("Dev: GERSYS BC3450\n");
275 void flash_preinit(void)
278 * Now, when we are in RAM, enable flash write
279 * access for detection process.
280 * Note that CS_BOOT cannot be cleared when
281 * executing in flash.
283 #if defined(CONFIG_MGT5100)
284 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
285 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
287 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
292 static struct pci_controller hose;
294 extern void pci_mpc5xxx_init(struct pci_controller *);
296 void pci_init_board(void)
298 pci_mpc5xxx_init(&hose);
302 #if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
303 #define GPIO_PSC1_4 0x01000000UL
305 void init_ide_reset (void)
307 debug ("init_ide_reset\n");
309 /* Configure PSC1_4 as GPIO output for ATA reset */
310 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
311 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
314 void ide_set_reset (int idereset)
316 debug ("ide_reset(%d)\n", idereset);
319 *(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
321 *(vu_long *) MPC5XXX_WU_GPIO_DATA |= GPIO_PSC1_4;
324 #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
328 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
329 * is left open, no keypress is detected.
331 int post_hotkeys_pressed(void)
333 struct mpc5xxx_gpio *gpio;
335 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
338 * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in
339 * CODEC or UART mode. Consumer IrDA should still be possible.
341 gpio->port_config &= ~(0x07000000);
342 gpio->port_config |= 0x03000000;
344 /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
345 gpio->simple_gpioe |= 0x20000000;
347 /* Configure GPIO_IRDA_1 as input */
348 gpio->simple_ddr &= ~(0x20000000);
350 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
354 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
356 void post_word_store (ulong a)
358 volatile ulong *save_addr =
359 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
364 ulong post_word_load (void)
366 volatile ulong *save_addr =
367 (volatile ulong *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE);
371 #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/
374 #ifdef CONFIG_BOARD_EARLY_INIT_R
375 int board_early_init_r (void)
377 #ifdef CONFIG_RTC_MPC5200
380 /* set to Wed Dec 31 19:00:00 1969 */
381 t.tm_sec = t.tm_min = 0;
389 #endif /* CONFIG_RTC_MPC5200 */
391 #ifdef CONFIG_PS2MULT
392 ps2mult_early_init();
393 #endif /* CONFIG_PS2MULT */
396 #endif /* CONFIG_BOARD_EARLY_INIT_R */
399 int last_stage_init (void)
402 * auto scan for really existing devices and re-set chip select
409 * Check for SRAM and SRAM size
412 /* save original SRAM content */
413 save = *(volatile u16 *)CFG_CS2_START;
416 /* write test pattern to SRAM */
417 *(volatile u16 *)CFG_CS2_START = 0xA5A5;
418 __asm__ volatile ("sync");
420 * Put a different pattern on the data lines: otherwise they may float
421 * long enough to read back what we wrote.
423 tmp = *(volatile u16 *)CFG_FLASH_BASE;
425 puts ("!! possible error in SRAM detection\n");
427 if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
428 /* no SRAM at all, disable cs */
429 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
430 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
431 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
433 __asm__ volatile ("sync");
434 } else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
435 /* make sure that we access a mirrored address */
436 *(volatile u16 *)CFG_CS2_START = 0x1111;
437 __asm__ volatile ("sync");
438 if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
439 /* SRAM size = 512 kByte */
440 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
442 __asm__ volatile ("sync");
443 puts ("SRAM: 512 kB\n");
446 puts ("!! possible error in SRAM detection\n");
448 puts ("SRAM: 1 MB\n");
450 /* restore origianl SRAM content */
452 *(volatile u16 *)CFG_CS2_START = save;
453 __asm__ volatile ("sync");
457 * Check for Grafic Controller
460 /* save origianl FB content */
461 save = *(volatile u16 *)CFG_CS1_START;
464 /* write test pattern to FB memory */
465 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
466 __asm__ volatile ("sync");
468 * Put a different pattern on the data lines: otherwise they may float
469 * long enough to read back what we wrote.
471 tmp = *(volatile u16 *)CFG_FLASH_BASE;
473 puts ("!! possible error in grafic controller detection\n");
475 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
476 /* no grafic controller at all, disable cs */
477 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
478 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
479 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
481 __asm__ volatile ("sync");
483 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
485 /* restore origianl FB content */
487 *(volatile u16 *)CFG_CS1_START = save;
488 __asm__ volatile ("sync");
494 #ifdef CONFIG_VIDEO_SM501
496 #define DISPLAY_WIDTH 640
497 #define DISPLAY_HEIGHT 480
499 #ifdef CONFIG_VIDEO_SM501_8BPP
500 #error CONFIG_VIDEO_SM501_8BPP not supported.
501 #endif /* CONFIG_VIDEO_SM501_8BPP */
503 #ifdef CONFIG_VIDEO_SM501_16BPP
504 #error CONFIG_VIDEO_SM501_16BPP not supported.
505 #endif /* CONFIG_VIDEO_SM501_16BPP */
507 #ifdef CONFIG_VIDEO_SM501_32BPP
508 static const SMI_REGS init_regs [] =
510 #if defined (CONFIG_BC3450_FP) && !defined (CONFIG_BC3450_CRT)
513 {0x00048, 0x00021807},
514 {0x0004C, 0x091a0a01},
516 {0x00040, 0x00021807},
517 {0x00044, 0x091a0a01},
519 {0x80000, 0x01013106},
520 {0x80004, 0xc428bb17},
521 {0x80000, 0x03013106},
522 {0x8000C, 0x00000000},
523 {0x80010, 0x0a000a00},
524 {0x80014, 0x02800000},
525 {0x80018, 0x01e00000},
526 {0x8001C, 0x00000000},
527 {0x80020, 0x01e00280},
528 {0x80024, 0x02fa027f},
529 {0x80028, 0x004a028b},
530 {0x8002C, 0x020c01df},
531 {0x80030, 0x000201e9},
532 {0x80200, 0x00010200},
533 {0x80000, 0x0f013106},
534 #elif defined (CONFIG_BC3450_CRT) && !defined (CONFIG_BC3450_FP)
537 {0x00048, 0x00021807},
538 {0x0004C, 0x10090a01},
540 {0x00040, 0x00021807},
541 {0x00044, 0x10090a01},
543 {0x80200, 0x00010000},
545 {0x80208, 0x0A000A00},
546 {0x8020C, 0x02fa027f},
547 {0x80210, 0x004a028b},
548 {0x80214, 0x020c01df},
549 {0x80218, 0x000201e9},
550 {0x80200, 0x00013306},
551 #else /* panel + CRT */
553 {0x00048, 0x00021807},
554 {0x0004C, 0x091a0a01},
556 {0x00040, 0x00021807},
557 {0x00044, 0x091a0a01},
559 {0x80000, 0x0f013106},
560 {0x80004, 0xc428bb17},
561 {0x8000C, 0x00000000},
562 {0x80010, 0x0a000a00},
563 {0x80014, 0x02800000},
564 {0x80018, 0x01e00000},
565 {0x8001C, 0x00000000},
566 {0x80020, 0x01e00280},
567 {0x80024, 0x02fa027f},
568 {0x80028, 0x004a028b},
569 {0x8002C, 0x020c01df},
570 {0x80030, 0x000201e9},
571 {0x80200, 0x00010000},
575 #endif /* CONFIG_VIDEO_SM501_32BPP */
577 #ifdef CONFIG_CONSOLE_EXTRA_INFO
579 * Return text to be printed besides the logo.
581 void video_get_info_str (int line_number, char *info)
583 if (line_number == 1) {
584 #if defined (CONFIG_TQM5200)
585 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
587 #error No supported board selected
588 #endif /* CONFIG_TQM5200 */
590 #if defined (CONFIG_BC3450)
591 } else if (line_number == 2) {
592 strcpy (info, " Dev: GERSYS BC3450");
593 #endif /* CONFIG_BC3450 */
602 * Returns SM501 register base address. First thing called in the
603 * driver. Checks if SM501 is physically present.
605 unsigned int board_video_init (void)
611 * Check for Grafic Controller
614 /* save origianl FB content */
615 save = *(volatile u16 *)CFG_CS1_START;
618 /* write test pattern to FB memory */
619 *(volatile u16 *)CFG_CS1_START = 0xA5A5;
620 __asm__ volatile ("sync");
622 * Put a different pattern on the data lines: otherwise they may float
623 * long enough to read back what we wrote.
625 tmp = *(volatile u16 *)CFG_FLASH_BASE;
627 puts ("!! possible error in grafic controller detection\n");
629 if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
630 /* no grafic controller found */
634 ret = SM501_MMIO_BASE;
638 *(volatile u16 *)CFG_CS1_START = save;
639 __asm__ volatile ("sync");
645 * Returns SM501 framebuffer address
647 unsigned int board_video_get_fb (void)
649 return SM501_FB_BASE;
653 * Called after initializing the SM501 and before clearing the screen.
655 void board_validate_screen (unsigned int base)
660 * Return a pointer to the initialization sequence.
662 const SMI_REGS *board_get_regs (void)
667 int board_get_width (void)
669 return DISPLAY_WIDTH;
672 int board_get_height (void)
674 return DISPLAY_HEIGHT;
677 #endif /* CONFIG_VIDEO_SM501 */