1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/sys_proto.h>
17 #include <asm/mach-imx/iomux-v3.h>
18 #include <asm/mach-imx/mxc_i2c.h>
19 #include <asm/mach-imx/boot_mode.h>
21 #include <fsl_esdhc_imx.h>
25 #include <linux/delay.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
30 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
33 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
35 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
36 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
38 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
40 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
44 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
49 iomux_v3_cfg_t const uart1_pads[] = {
50 MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
54 iomux_v3_cfg_t const uart2_pads[] = {
55 MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
56 MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
59 iomux_v3_cfg_t const uart4_pads[] = {
60 MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
61 MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
64 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
66 struct i2c_pads_info i2c_pad_info0 = {
68 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
69 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
70 .gp = IMX_GPIO_NR(5, 27)
73 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
74 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
75 .gp = IMX_GPIO_NR(5, 26)
79 struct i2c_pads_info i2c_pad_info2 = {
81 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
82 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
83 .gp = IMX_GPIO_NR(1, 3)
86 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
87 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
88 .gp = IMX_GPIO_NR(7, 11)
92 iomux_v3_cfg_t const usdhc3_pads[] = {
93 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
97 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
98 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
99 MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
102 iomux_v3_cfg_t const enet_pads1[] = {
103 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
108 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
110 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 /* pin 35 - 1 (PHY_AD2) on reset */
113 MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
114 /* pin 32 - 1 - (MODE0) all */
115 MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
116 /* pin 31 - 1 - (MODE1) all */
117 MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
118 /* pin 28 - 1 - (MODE2) all */
119 MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
120 /* pin 27 - 1 - (MODE3) all */
121 MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
122 /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
123 MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
124 /* pin 42 PHY nRST */
125 MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
128 iomux_v3_cfg_t const enet_pads2[] = {
129 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
130 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
131 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
132 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
133 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
134 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
137 iomux_v3_cfg_t nfc_pads[] = {
138 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
139 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
140 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
141 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
142 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
143 MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
144 MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
145 MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
146 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
147 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
148 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
149 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
150 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
151 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
152 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
153 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
154 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
155 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
156 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
159 static void setup_gpmi_nand(void)
161 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
163 /* config gpmi nand iomux */
164 imx_iomux_v3_setup_multiple_pads(nfc_pads,
165 ARRAY_SIZE(nfc_pads));
167 /* config gpmi and bch clock to 100 MHz */
168 clrsetbits_le32(&mxc_ccm->cs2cdr,
169 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
170 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
171 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
172 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
173 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
174 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
176 /* enable gpmi and bch clock gating */
177 setbits_le32(&mxc_ccm->CCGR4,
178 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
179 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
180 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
181 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
182 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
184 /* enable apbh clock gating */
185 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
188 static void setup_iomux_enet(void)
190 gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
191 gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
192 gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
193 gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
194 gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
195 gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
196 imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
197 gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
199 /* Need delay 10ms according to KSZ9021 spec */
201 gpio_set_value(IMX_GPIO_NR(3, 23), 1);
203 imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
206 static void setup_iomux_uart(void)
208 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
209 imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
210 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
213 #ifdef CONFIG_USB_EHCI_MX6
214 int board_ehci_hcd_init(int port)
221 #ifdef CONFIG_FSL_ESDHC_IMX
222 struct fsl_esdhc_cfg usdhc_cfg[1] = {
223 { USDHC3_BASE_ADDR },
226 int board_mmc_getcd(struct mmc *mmc)
228 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
230 if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
231 gpio_direction_input(IMX_GPIO_NR(7, 0));
232 return !gpio_get_value(IMX_GPIO_NR(7, 0));
238 int board_mmc_init(bd_t *bis)
241 * Only one USDHC controller on titianium
243 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
244 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
246 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
250 int board_phy_config(struct phy_device *phydev)
252 /* min rx data delay */
253 ksz9021_phy_extended_write(phydev,
254 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
255 /* min tx data delay */
256 ksz9021_phy_extended_write(phydev,
257 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
258 /* max rx/tx clock delay, min rx/tx control */
259 ksz9021_phy_extended_write(phydev,
260 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
261 if (phydev->drv->config)
262 phydev->drv->config(phydev);
267 int board_eth_init(bd_t *bis)
271 return cpu_eth_init(bis);
274 int board_early_init_f(void)
283 /* address of boot parameters */
284 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
286 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
287 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
296 puts("Board: Titanium\n");
301 #ifdef CONFIG_CMD_BMODE
302 static const struct boot_mode board_boot_modes[] = {
304 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
305 /* 4 bit bus width */
306 { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
307 { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
312 int misc_init_r(void)
314 #ifdef CONFIG_CMD_BMODE
315 add_board_boot_modes(board_boot_modes);