1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
10 #include <asm/arch/crm_regs.h>
15 #define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
16 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
18 #define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
19 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
21 #define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
22 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
24 #define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
25 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
27 #define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
28 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
31 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
32 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
34 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
35 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
36 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
37 #define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
38 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
39 PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
41 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
42 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
46 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
50 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
51 #define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL)
55 int platinum_setup_enet(void);
56 int platinum_setup_i2c(void);
57 int platinum_setup_spi(void);
58 int platinum_setup_uart(void);
59 int platinum_phy_config(struct phy_device *phydev);
60 int platinum_init_gpio(void);
61 int platinum_init_usb(void);
62 int platinum_init_finished(void);
64 static inline void ccgr_init(void)
66 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
68 writel(0x00C03F3F, &ccm->CCGR0);
69 writel(0x0030FC03, &ccm->CCGR1);
70 writel(0x0FFFC000, &ccm->CCGR2);
71 writel(0x3FF00000, &ccm->CCGR3);
72 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
73 writel(0x0F0000C3, &ccm->CCGR5);
74 writel(0x000003FF, &ccm->CCGR6);
77 #endif /* _PLATINUM_H_ */