3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
5 * Copyright 2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/immap_fsl_pci.h>
36 #include <fdt_support.h>
38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
39 extern void ddr_enable_ecc(unsigned int dram_size);
42 extern long int spd_sdram(void);
43 long int fixed_sdram(void);
45 int board_early_init_f (void)
52 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
53 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
54 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
56 if ((uint)&gur->porpllsr != 0xe00e0000) {
57 printf("immap size error %x\n",&gur->porpllsr);
59 printf ("Board: ATUM8548\n");
61 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
62 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
63 ecm->eedr = 0xffffffff; /* Clear ecm errors */
64 ecm->eeer = 0xffffffff; /* Enable ecm errors */
69 #if !defined(CONFIG_SPD_EEPROM)
70 /*************************************************************************
71 * fixed sdram init -- doesn't use serial presence detect.
72 ************************************************************************/
73 long int fixed_sdram (void)
75 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
77 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
78 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
79 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
80 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
81 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
82 ddr->sdram_mode = CFG_DDR_MODE;
83 ddr->sdram_interval = CFG_DDR_INTERVAL;
84 #if defined (CONFIG_DDR_ECC)
85 ddr->err_disable = 0x0000000D;
86 ddr->err_sbe = 0x00ff0000;
88 asm("sync;isync;msync");
90 #if defined (CONFIG_DDR_ECC)
91 /* Enable ECC checking */
92 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
94 ddr->sdram_cfg = CFG_DDR_CONTROL;
96 asm("sync; isync; msync");
98 return CFG_SDRAM_SIZE * 1024 * 1024;
100 #endif /* !defined(CONFIG_SPD_EEPROM) */
103 initdram(int board_type)
107 puts("Initializing\n");
109 #if defined(CONFIG_SPD_EEPROM)
111 dram_size = spd_sdram ();
113 puts("fixed_sdram\n");
114 dram_size = fixed_sdram ();
117 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
119 * Initialize and enable DDR ECC.
121 ddr_enable_ecc(dram_size);
127 #if defined(CFG_DRAM_TEST)
131 uint *pstart = (uint *) CFG_MEMTEST_START;
132 uint *pend = (uint *) CFG_MEMTEST_END;
135 printf("Testing DRAM from 0x%08x to 0x%08x\n",
139 printf("DRAM test phase 1:\n");
140 for (p = pstart; p < pend; p++) {
141 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
145 for (p = pstart; p < pend; p++) {
146 if (*p != 0xaaaaaaaa) {
147 printf ("DRAM test fails at: %08x\n", (uint) p);
152 printf("DRAM test phase 2:\n");
153 for (p = pstart; p < pend; p++)
156 for (p = pstart; p < pend; p++) {
157 if (*p != 0x55555555) {
158 printf ("DRAM test fails at: %08x\n", (uint) p);
163 printf("DRAM test passed.\n");
169 static struct pci_controller pci1_hose;
173 static struct pci_controller pci2_hose;
177 static struct pci_controller pcie1_hose;
180 int first_free_busno=0;
185 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
187 uint devdisr = gur->devdisr;
188 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
189 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
191 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
192 devdisr, io_sel, host_agent);
194 /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
195 gur->clkocr |= MPC85xx_ATUM_CLKOCR;
198 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
199 printf (" eTSEC1 is in sgmii mode.\n");
200 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
201 printf (" eTSEC2 is in sgmii mode.\n");
202 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
203 printf (" eTSEC3 is in sgmii mode.\n");
204 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
205 printf (" eTSEC4 is in sgmii mode.\n");
210 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
211 extern void fsl_pci_init(struct pci_controller *hose);
212 struct pci_controller *hose = &pcie1_hose;
213 int pcie_ep = (host_agent == 5);
214 int pcie_configured = io_sel & 6;
216 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
217 printf ("\n PCIE1 connected to slot as %s (base address %x)",
218 pcie_ep ? "End Point" : "Root Complex",
220 if (pci->pme_msg_det) {
221 pci->pme_msg_det = 0xffffffff;
222 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
227 pci_set_region(hose->regions + 0,
231 PCI_REGION_MEM | PCI_REGION_MEMORY);
233 /* outbound memory */
234 pci_set_region(hose->regions + 1,
241 pci_set_region(hose->regions + 2,
247 hose->region_count = 3;
248 #ifdef CFG_PCIE1_MEM_BASE2
249 /* outbound memory */
250 pci_set_region(hose->regions + 3,
255 hose->region_count++;
257 hose->first_busno=first_free_busno;
259 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
263 first_free_busno=hose->last_busno+1;
264 printf(" PCIE1 on bus %02x - %02x\n",
265 hose->first_busno,hose->last_busno);
268 printf (" PCIE1: disabled\n");
273 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
278 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
279 extern void fsl_pci_init(struct pci_controller *hose);
280 struct pci_controller *hose = &pci1_hose;
282 uint pci_agent = (host_agent == 6);
283 uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
284 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
285 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
286 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
288 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
289 printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
291 (pci_speed == 33333000) ? "33" :
292 (pci_speed == 66666000) ? "66" : "unknown",
293 pci_clk_sel ? "sync" : "async",
294 pci_agent ? "agent" : "host",
295 pci_arb ? "arbiter" : "external-arbiter",
300 pci_set_region(hose->regions + 0,
304 PCI_REGION_MEM | PCI_REGION_MEMORY);
306 /* outbound memory */
307 pci_set_region(hose->regions + 1,
314 pci_set_region(hose->regions + 2,
319 hose->region_count = 3;
320 hose->first_busno=first_free_busno;
321 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
324 first_free_busno=hose->last_busno+1;
325 printf ("PCI1 on bus %02x - %02x\n",
326 hose->first_busno,hose->last_busno);
328 printf (" PCI1: disabled\n");
332 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
337 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
338 extern void fsl_pci_init(struct pci_controller *hose);
339 struct pci_controller *hose = &pci2_hose;
341 if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
342 pci_set_region(hose->regions + 0,
346 PCI_REGION_MEM | PCI_REGION_MEMORY);
348 pci_set_region(hose->regions + 1,
354 pci_set_region(hose->regions + 2,
359 hose->region_count = 3;
360 hose->first_busno=first_free_busno;
361 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
364 first_free_busno=hose->last_busno+1;
365 printf ("PCI2 on bus %02x - %02x\n",
366 hose->first_busno,hose->last_busno);
368 printf (" PCI2: disabled\n");
372 gur->devdisr |= MPC85xx_DEVDISR_PCI2;
377 int last_stage_init(void)
379 int ic = icache_status ();
380 printf ("icache_status: %d\n", ic);
384 #if defined(CONFIG_OF_BOARD_SETUP)
387 ft_board_setup(void *blob, bd_t *bd)
392 ft_cpu_setup(blob, bd);
394 node = fdt_path_offset(blob, "/aliases");
398 path = fdt_getprop(blob, node, "pci0", NULL);
400 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
401 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
405 path = fdt_getprop(blob, node, "pci1", NULL);
407 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
408 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
412 path = fdt_getprop(blob, node, "pci2", NULL);
414 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
415 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);