3 * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
5 * Copyright 2007 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/immap_fsl_pci.h>
32 #include <asm/fsl_ddr_sdram.h>
35 #include <spd_sdram.h>
38 #include <fdt_support.h>
40 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
41 extern void ddr_enable_ecc(unsigned int dram_size);
44 long int fixed_sdram(void);
46 int board_early_init_f (void)
53 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
54 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
55 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
57 if ((uint)&gur->porpllsr != 0xe00e0000) {
58 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
60 printf ("Board: ATUM8548\n");
62 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
63 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
64 ecm->eedr = 0xffffffff; /* Clear ecm errors */
65 ecm->eeer = 0xffffffff; /* Enable ecm errors */
70 #if !defined(CONFIG_SPD_EEPROM)
71 /*************************************************************************
72 * fixed sdram init -- doesn't use serial presence detect.
73 ************************************************************************/
74 long int fixed_sdram (void)
76 volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
78 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
79 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
80 ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
81 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
82 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
83 ddr->sdram_mode = CFG_DDR_MODE;
84 ddr->sdram_interval = CFG_DDR_INTERVAL;
85 #if defined (CONFIG_DDR_ECC)
86 ddr->err_disable = 0x0000000D;
87 ddr->err_sbe = 0x00ff0000;
89 asm("sync;isync;msync");
91 #if defined (CONFIG_DDR_ECC)
92 /* Enable ECC checking */
93 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
95 ddr->sdram_cfg = CFG_DDR_CONTROL;
97 asm("sync; isync; msync");
99 return CFG_SDRAM_SIZE * 1024 * 1024;
101 #endif /* !defined(CONFIG_SPD_EEPROM) */
104 initdram(int board_type)
108 puts("Initializing\n");
110 #if defined(CONFIG_SPD_EEPROM)
111 puts("fsl_ddr_sdram\n");
112 dram_size = fsl_ddr_sdram();
113 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
114 dram_size *= 0x100000;
116 puts("fixed_sdram\n");
117 dram_size = fixed_sdram ();
120 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
122 * Initialize and enable DDR ECC.
124 ddr_enable_ecc(dram_size);
130 #if defined(CFG_DRAM_TEST)
134 uint *pstart = (uint *) CFG_MEMTEST_START;
135 uint *pend = (uint *) CFG_MEMTEST_END;
138 printf("Testing DRAM from 0x%08x to 0x%08x\n",
142 printf("DRAM test phase 1:\n");
143 for (p = pstart; p < pend; p++) {
144 printf ("DRAM test attempting to write 0xaaaaaaaa at: %08x\n", (uint) p);
148 for (p = pstart; p < pend; p++) {
149 if (*p != 0xaaaaaaaa) {
150 printf ("DRAM test fails at: %08x\n", (uint) p);
155 printf("DRAM test phase 2:\n");
156 for (p = pstart; p < pend; p++)
159 for (p = pstart; p < pend; p++) {
160 if (*p != 0x55555555) {
161 printf ("DRAM test fails at: %08x\n", (uint) p);
166 printf("DRAM test passed.\n");
172 static struct pci_controller pci1_hose;
176 static struct pci_controller pci2_hose;
180 static struct pci_controller pcie1_hose;
183 int first_free_busno=0;
188 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
190 uint devdisr = gur->devdisr;
191 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
192 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
194 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
195 devdisr, io_sel, host_agent);
197 /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */
198 gur->clkocr |= MPC85xx_ATUM_CLKOCR;
201 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
202 printf (" eTSEC1 is in sgmii mode.\n");
203 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
204 printf (" eTSEC2 is in sgmii mode.\n");
205 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
206 printf (" eTSEC3 is in sgmii mode.\n");
207 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
208 printf (" eTSEC4 is in sgmii mode.\n");
213 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
214 extern void fsl_pci_init(struct pci_controller *hose);
215 struct pci_controller *hose = &pcie1_hose;
216 int pcie_ep = (host_agent == 5);
217 int pcie_configured = io_sel & 6;
219 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
220 printf ("\n PCIE1 connected to slot as %s (base address %x)",
221 pcie_ep ? "End Point" : "Root Complex",
223 if (pci->pme_msg_det) {
224 pci->pme_msg_det = 0xffffffff;
225 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
230 pci_set_region(hose->regions + 0,
234 PCI_REGION_MEM | PCI_REGION_MEMORY);
236 /* outbound memory */
237 pci_set_region(hose->regions + 1,
244 pci_set_region(hose->regions + 2,
250 hose->region_count = 3;
251 #ifdef CFG_PCIE1_MEM_BASE2
252 /* outbound memory */
253 pci_set_region(hose->regions + 3,
258 hose->region_count++;
260 hose->first_busno=first_free_busno;
262 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
266 first_free_busno=hose->last_busno+1;
267 printf(" PCIE1 on bus %02x - %02x\n",
268 hose->first_busno,hose->last_busno);
271 printf (" PCIE1: disabled\n");
276 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
281 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
282 extern void fsl_pci_init(struct pci_controller *hose);
283 struct pci_controller *hose = &pci1_hose;
285 uint pci_agent = (host_agent == 6);
286 uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */
287 uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
288 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
289 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
291 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
292 printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
294 (pci_speed == 33333000) ? "33" :
295 (pci_speed == 66666000) ? "66" : "unknown",
296 pci_clk_sel ? "sync" : "async",
297 pci_agent ? "agent" : "host",
298 pci_arb ? "arbiter" : "external-arbiter",
303 pci_set_region(hose->regions + 0,
307 PCI_REGION_MEM | PCI_REGION_MEMORY);
309 /* outbound memory */
310 pci_set_region(hose->regions + 1,
317 pci_set_region(hose->regions + 2,
322 hose->region_count = 3;
323 hose->first_busno=first_free_busno;
324 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
327 first_free_busno=hose->last_busno+1;
328 printf ("PCI1 on bus %02x - %02x\n",
329 hose->first_busno,hose->last_busno);
331 printf (" PCI1: disabled\n");
335 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
340 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
341 extern void fsl_pci_init(struct pci_controller *hose);
342 struct pci_controller *hose = &pci2_hose;
344 if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
345 pci_set_region(hose->regions + 0,
349 PCI_REGION_MEM | PCI_REGION_MEMORY);
351 pci_set_region(hose->regions + 1,
357 pci_set_region(hose->regions + 2,
362 hose->region_count = 3;
363 hose->first_busno=first_free_busno;
364 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
367 first_free_busno=hose->last_busno+1;
368 printf ("PCI2 on bus %02x - %02x\n",
369 hose->first_busno,hose->last_busno);
371 printf (" PCI2: disabled\n");
375 gur->devdisr |= MPC85xx_DEVDISR_PCI2;
380 int last_stage_init(void)
382 int ic = icache_status ();
383 printf ("icache_status: %d\n", ic);
387 #if defined(CONFIG_OF_BOARD_SETUP)
390 ft_board_setup(void *blob, bd_t *bd)
395 ft_cpu_setup(blob, bd);
397 node = fdt_path_offset(blob, "/aliases");
401 path = fdt_getprop(blob, node, "pci0", NULL);
403 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
404 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
408 path = fdt_getprop(blob, node, "pci1", NULL);
410 tmp[1] = pci2_hose.last_busno - pci2_hose.first_busno;
411 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
415 path = fdt_getprop(blob, node, "pci2", NULL);
417 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
418 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);