2 * Copyright (C) 2014 Atmel
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/at91_rstc.h>
12 #include <asm/arch/atmel_mpddrc.h>
13 #include <asm/arch/gpio.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/sama5d3_smc.h>
16 #include <asm/arch/sama5d4.h>
17 #include <atmel_hlcdc.h>
18 #include <debug_uart.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #ifdef CONFIG_NAND_ATMEL
26 static void sama5d4ek_nand_hw_init(void)
28 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
30 at91_periph_clk_enable(ATMEL_ID_SMC);
32 /* Configure SMC CS3 for NAND */
33 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
34 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
36 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
37 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
39 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
41 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
42 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
43 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)|
44 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
45 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
46 AT91_SMC_MODE_EXNW_DISABLE |
48 AT91_SMC_MODE_TDF_CYCLE(3),
51 at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */
52 at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */
53 at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */
54 at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */
55 at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */
56 at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */
57 at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */
58 at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */
59 at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */
60 at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */
61 at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */
62 at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */
63 at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */
64 at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */
69 static void sama5d4ek_usb_hw_init(void)
71 at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
72 at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
73 at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
78 vidinfo_t panel_info = {
85 .vl_left_margin = 128,
88 .vl_upper_margin = 23,
89 .vl_lower_margin = 22,
90 .mmio = ATMEL_BASE_LCDC,
93 /* No power up/down pin for the LCD pannel */
94 void lcd_enable(void) { /* Empty! */ }
95 void lcd_disable(void) { /* Empty! */ }
97 unsigned int has_lcdc(void)
102 static void sama5d4ek_lcd_hw_init(void)
104 at91_pio3_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */
105 at91_pio3_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */
106 at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */
107 at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */
108 at91_pio3_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */
109 at91_pio3_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */
111 at91_pio3_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */
112 at91_pio3_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */
113 at91_pio3_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */
114 at91_pio3_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */
115 at91_pio3_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */
116 at91_pio3_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */
118 at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */
119 at91_pio3_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */
120 at91_pio3_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */
121 at91_pio3_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */
122 at91_pio3_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */
123 at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */
125 at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */
126 at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */
127 at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */
128 at91_pio3_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */
129 at91_pio3_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */
130 at91_pio3_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */
133 at91_periph_clk_enable(ATMEL_ID_LCDC);
136 #ifdef CONFIG_LCD_INFO
137 void lcd_show_board_info(void)
139 ulong dram_size, nand_size;
143 lcd_printf("%s\n", U_BOOT_VERSION);
144 lcd_printf("2014 ATMEL Corp\n");
145 lcd_printf("at91@atmel.com\n");
146 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
147 strmhz(temp, get_cpu_clk_rate()));
150 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
151 dram_size += gd->bd->bi_dram[i].size;
154 #ifdef CONFIG_NAND_ATMEL
155 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
156 nand_size += nand_info[i]->size;
158 lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
159 dram_size >> 20, nand_size >> 20);
161 #endif /* CONFIG_LCD_INFO */
163 #endif /* CONFIG_LCD */
165 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
166 static void sama5d4ek_serial3_hw_init(void)
168 at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */
169 at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */
172 at91_periph_clk_enable(ATMEL_ID_USART3);
175 void board_debug_uart_init(void)
177 sama5d4ek_serial3_hw_init();
181 #ifdef CONFIG_BOARD_EARLY_INIT_F
182 int board_early_init_f(void)
184 #ifdef CONFIG_DEBUG_UART
193 /* adress of boot parameters */
194 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
196 #ifdef CONFIG_NAND_ATMEL
197 sama5d4ek_nand_hw_init();
200 sama5d4ek_lcd_hw_init();
202 #ifdef CONFIG_CMD_USB
203 sama5d4ek_usb_hw_init();
211 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
212 CONFIG_SYS_SDRAM_SIZE);
217 #ifdef CONFIG_SPL_BUILD
218 void spl_board_init(void)
220 #if CONFIG_SYS_USE_NANDFLASH
221 sama5d4ek_nand_hw_init();
225 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
227 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
229 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
230 ATMEL_MPDDRC_CR_NR_ROW_14 |
231 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
232 ATMEL_MPDDRC_CR_NB_8BANKS |
233 ATMEL_MPDDRC_CR_NDQS_DISABLED |
234 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
235 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
239 ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
240 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
241 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
242 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
243 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
244 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
245 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
246 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
248 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
249 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
250 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
251 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
253 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
254 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
255 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
256 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
257 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
262 struct atmel_mpddrc_config ddr2;
266 /* Enable MPDDR clock */
267 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
268 at91_system_clk_enable(AT91_PMC_DDR);
270 /* DDRAM2 Controller initialize */
271 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
274 void at91_pmc_init(void)
278 tmp = AT91_PMC_PLLAR_29 |
279 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
280 AT91_PMC_PLLXR_MUL(87) |
281 AT91_PMC_PLLXR_DIV(1);
284 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
286 tmp = AT91_PMC_MCKR_H32MXDIV |
287 AT91_PMC_MCKR_PLLADIV_2 |
288 AT91_PMC_MCKR_MDIV_3 |
289 AT91_PMC_MCKR_CSS_PLLA;