board/atmel/sama5d4_xplained/sama5d4_xplained.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Atmel
   4  *                    Bo Shen <voice.shen@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/at91_common.h>
  11 #include <asm/arch/at91_rstc.h>
  12 #include <asm/arch/atmel_mpddrc.h>
  13 #include <asm/arch/gpio.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/sama5d3_smc.h>
  16 #include <asm/arch/sama5d4.h>
  17 #include <debug_uart.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 extern void at91_pda_detect(void);
  22
  23 #ifdef CONFIG_NAND_ATMEL
  24 static void sama5d4_xplained_nand_hw_init(void)
  25 {
  26         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  27
  28         at91_periph_clk_enable(ATMEL_ID_SMC);
  29
  30         /* Configure SMC CS3 for NAND */
  31         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  32                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
  33                &smc->cs[3].setup);
  34         writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) |
  35                AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
  36                &smc->cs[3].pulse);
  37         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  38                &smc->cs[3].cycle);
  39         writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
  40                AT91_SMC_TIMINGS_TAR(2)  | AT91_SMC_TIMINGS_TRR(3)   |
  41                AT91_SMC_TIMINGS_TWB(7)  | AT91_SMC_TIMINGS_RBNSEL(3)|
  42                AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
  43         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  44                AT91_SMC_MODE_EXNW_DISABLE |
  45                AT91_SMC_MODE_DBW_8 |
  46                AT91_SMC_MODE_TDF_CYCLE(3),
  47                &smc->cs[3].mode);
  48
  49         at91_pio3_set_a_periph(AT91_PIO_PORTC, 5, 0);   /* D0 */
  50         at91_pio3_set_a_periph(AT91_PIO_PORTC, 6, 0);   /* D1 */
  51         at91_pio3_set_a_periph(AT91_PIO_PORTC, 7, 0);   /* D2 */
  52         at91_pio3_set_a_periph(AT91_PIO_PORTC, 8, 0);   /* D3 */
  53         at91_pio3_set_a_periph(AT91_PIO_PORTC, 9, 0);   /* D4 */
  54         at91_pio3_set_a_periph(AT91_PIO_PORTC, 10, 0);  /* D5 */
  55         at91_pio3_set_a_periph(AT91_PIO_PORTC, 11, 0);  /* D6 */
  56         at91_pio3_set_a_periph(AT91_PIO_PORTC, 12, 0);  /* D7 */
  57         at91_pio3_set_a_periph(AT91_PIO_PORTC, 13, 0);  /* RE */
  58         at91_pio3_set_a_periph(AT91_PIO_PORTC, 14, 0);  /* WE */
  59         at91_pio3_set_a_periph(AT91_PIO_PORTC, 15, 1);  /* NCS */
  60         at91_pio3_set_a_periph(AT91_PIO_PORTC, 16, 1);  /* RDY */
  61         at91_pio3_set_a_periph(AT91_PIO_PORTC, 17, 1);  /* ALE */
  62         at91_pio3_set_a_periph(AT91_PIO_PORTC, 18, 1);  /* CLE */
  63 }
  64 #endif
  65
  66 #ifdef CONFIG_CMD_USB
  67 static void sama5d4_xplained_usb_hw_init(void)
  68 {
  69         at91_set_pio_output(AT91_PIO_PORTE, 11, 1);
  70         at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
  71 }
  72 #endif
  73
  74 #ifdef CONFIG_BOARD_LATE_INIT
  75 int board_late_init(void)
  76 {
  77         at91_pda_detect();
  78 #ifdef CONFIG_DM_VIDEO
  79         at91_video_show_board_info();
  80 #endif
  81         return 0;
  82 }
  83 #endif
  84
  85 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  86 static void sama5d4_xplained_serial3_hw_init(void)
  87 {
  88         at91_pio3_set_b_periph(AT91_PIO_PORTE, 17, 1);  /* TXD3 */
  89         at91_pio3_set_b_periph(AT91_PIO_PORTE, 16, 0);  /* RXD3 */
  90
  91         /* Enable clock */
  92         at91_periph_clk_enable(ATMEL_ID_USART3);
  93 }
  94
  95 void board_debug_uart_init(void)
  96 {
  97         sama5d4_xplained_serial3_hw_init();
  98 }
  99 #endif
 100
 101 #ifdef CONFIG_BOARD_EARLY_INIT_F
 102 int board_early_init_f(void)
 103 {
 104 #ifdef CONFIG_DEBUG_UART
 105         debug_uart_init();
 106 #endif
 107         return 0;
 108 }
 109 #endif
 110
 111 #define AT24MAC_MAC_OFFSET      0x9a
 112
 113 #ifdef CONFIG_MISC_INIT_R
 114 int misc_init_r(void)
 115 {
 116 #ifdef CONFIG_I2C_EEPROM
 117         at91_set_ethaddr(AT24MAC_MAC_OFFSET);
 118 #endif
 119         return 0;
 120 }
 121 #endif
 122
 123 int board_init(void)
 124 {
 125         /* adress of boot parameters */
 126         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 127
 128 #ifdef CONFIG_NAND_ATMEL
 129         sama5d4_xplained_nand_hw_init();
 130 #endif
 131 #ifdef CONFIG_CMD_USB
 132         sama5d4_xplained_usb_hw_init();
 133 #endif
 134
 135         return 0;
 136 }
 137
 138 int dram_init(void)
 139 {
 140         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 141                                     CONFIG_SYS_SDRAM_SIZE);
 142         return 0;
 143 }
 144
 145 /* SPL */
 146 #ifdef CONFIG_SPL_BUILD
 147 void spl_board_init(void)
 148 {
 149 #if CONFIG_NAND_BOOT
 150         sama5d4_xplained_nand_hw_init();
 151 #endif
 152 }
 153
 154 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 155 {
 156         ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 157
 158         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 159                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 160                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 161                     ATMEL_MPDDRC_CR_NB_8BANKS |
 162                     ATMEL_MPDDRC_CR_NDQS_DISABLED |
 163                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 164                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 165
 166         ddr2->rtr = 0x2b0;
 167
 168         ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 169                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 170                       3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 171                       10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 172                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 173                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 174                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 175                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 176
 177         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 178                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 179                       25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 180                       23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 181
 182         ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
 183                       2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 184                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 185                       2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 186                       8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 187 }
 188
 189 void mem_init(void)
 190 {
 191         struct atmel_mpddrc_config ddr2;
 192
 193         ddr2_conf(&ddr2);
 194
 195         /* Enable MPDDR clock */
 196         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 197         at91_system_clk_enable(AT91_PMC_DDR);
 198
 199         /* DDRAM2 Controller initialize */
 200         ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
 201 }
 202
 203 void at91_pmc_init(void)
 204 {
 205         u32 tmp;
 206
 207         tmp = AT91_PMC_PLLAR_29 |
 208               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 209               AT91_PMC_PLLXR_MUL(87) |
 210               AT91_PMC_PLLXR_DIV(1);
 211         at91_plla_init(tmp);
 212
 213         at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
 214
 215         tmp = AT91_PMC_MCKR_H32MXDIV |
 216               AT91_PMC_MCKR_PLLADIV_2 |
 217               AT91_PMC_MCKR_MDIV_3 |
 218               AT91_PMC_MCKR_CSS_PLLA;
 219         at91_mck_init(tmp);
 220 }
 221 #endif