2 * Copyright (C) 2012 - 2013 Atmel Corporation
3 * Bo Shen <voice.shen@atmel.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/sama5d3_smc.h>
12 #include <asm/arch/at91_common.h>
13 #include <asm/arch/at91_rstc.h>
14 #include <asm/arch/gpio.h>
15 #include <asm/arch/clk.h>
17 #include <linux/ctype.h>
18 #include <atmel_hlcdc.h>
19 #include <atmel_mci.h>
25 #include <asm/arch/atmel_mpddrc.h>
26 #include <asm/arch/at91_wdt.h>
28 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
29 #include <asm/arch/atmel_usba_udc.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 /* ------------------------------------------------------------------------- */
36 * Miscelaneous platform dependent initialisations
39 #ifdef CONFIG_NAND_ATMEL
40 void sama5d3xek_nand_hw_init(void)
42 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
44 at91_periph_clk_enable(ATMEL_ID_SMC);
46 /* Configure SMC CS3 for NAND/SmartMedia */
47 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
48 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
50 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
51 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
53 writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
55 writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
56 AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
57 AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3)|
58 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61 #ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 |
63 #else /* CONFIG_SYS_NAND_DBW_8 */
66 AT91_SMC_MODE_TDF_CYCLE(3),
71 #ifndef CONFIG_SYS_NO_FLASH
72 static void sama5d3xek_nor_hw_init(void)
74 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
76 at91_periph_clk_enable(ATMEL_ID_SMC);
78 /* Configure SMC CS0 for NOR flash */
79 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
80 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
82 writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
83 AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
85 writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
87 writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0) |
88 AT91_SMC_TIMINGS_TAR(0) | AT91_SMC_TIMINGS_TRR(0) |
89 AT91_SMC_TIMINGS_TWB(0) | AT91_SMC_TIMINGS_RBNSEL(0)|
90 AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[0].timings);
91 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
92 AT91_SMC_MODE_EXNW_DISABLE |
93 AT91_SMC_MODE_DBW_16 |
94 AT91_SMC_MODE_TDF_CYCLE(1),
97 /* Address pin (A1 ~ A23) configuration */
98 at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
99 at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
100 at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
101 at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
102 at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
103 at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
104 at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
105 at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
106 at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
107 at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
108 at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
109 at91_set_a_periph(AT91_PIO_PORTE, 12, 0);
110 at91_set_a_periph(AT91_PIO_PORTE, 13, 0);
111 at91_set_a_periph(AT91_PIO_PORTE, 14, 0);
112 at91_set_a_periph(AT91_PIO_PORTE, 15, 0);
113 at91_set_a_periph(AT91_PIO_PORTE, 16, 0);
114 at91_set_a_periph(AT91_PIO_PORTE, 17, 0);
115 at91_set_a_periph(AT91_PIO_PORTE, 18, 0);
116 at91_set_a_periph(AT91_PIO_PORTE, 19, 0);
117 at91_set_a_periph(AT91_PIO_PORTE, 20, 0);
118 at91_set_a_periph(AT91_PIO_PORTE, 21, 0);
119 at91_set_a_periph(AT91_PIO_PORTE, 22, 0);
120 at91_set_a_periph(AT91_PIO_PORTE, 23, 0);
121 /* CS0 pin configuration */
122 at91_set_a_periph(AT91_PIO_PORTE, 26, 0);
126 #ifdef CONFIG_CMD_USB
127 static void sama5d3xek_usb_hw_init(void)
129 at91_set_pio_output(AT91_PIO_PORTD, 25, 0);
130 at91_set_pio_output(AT91_PIO_PORTD, 26, 0);
131 at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
135 #ifdef CONFIG_GENERIC_ATMEL_MCI
136 static void sama5d3xek_mci_hw_init(void)
140 at91_set_pio_output(AT91_PIO_PORTB, 10, 0); /* MCI0 Power */
145 vidinfo_t panel_info = {
152 .vl_left_margin = 64,
153 .vl_right_margin = 64,
155 .vl_upper_margin = 22,
156 .vl_lower_margin = 21,
157 .mmio = ATMEL_BASE_LCDC,
160 void lcd_enable(void)
164 void lcd_disable(void)
168 static void sama5d3xek_lcd_hw_init(void)
170 gd->fb_base = CONFIG_SAMA5D3_LCD_BASE;
172 /* The higher 8 bit of LCD is board related */
173 at91_set_c_periph(AT91_PIO_PORTC, 14, 0); /* LCDD16 */
174 at91_set_c_periph(AT91_PIO_PORTC, 13, 0); /* LCDD17 */
175 at91_set_c_periph(AT91_PIO_PORTC, 12, 0); /* LCDD18 */
176 at91_set_c_periph(AT91_PIO_PORTC, 11, 0); /* LCDD19 */
177 at91_set_c_periph(AT91_PIO_PORTC, 10, 0); /* LCDD20 */
178 at91_set_c_periph(AT91_PIO_PORTC, 15, 0); /* LCDD21 */
179 at91_set_c_periph(AT91_PIO_PORTE, 27, 0); /* LCDD22 */
180 at91_set_c_periph(AT91_PIO_PORTE, 28, 0); /* LCDD23 */
182 /* Configure lower 16 bit of LCD and enable clock */
186 #ifdef CONFIG_LCD_INFO
190 void lcd_show_board_info(void)
197 lcd_printf("%s\n", U_BOOT_VERSION);
198 lcd_printf("(C) 2013 ATMEL Corp\n");
199 lcd_printf("at91@atmel.com\n");
200 lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
201 strmhz(temp, get_cpu_clk_rate()));
204 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
205 dram_size += gd->bd->bi_dram[i].size;
208 #ifdef CONFIG_NAND_ATMEL
209 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
210 nand_size += nand_info[i].size;
212 lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
213 dram_size >> 20, nand_size >> 20);
215 #endif /* CONFIG_LCD_INFO */
216 #endif /* CONFIG_LCD */
218 int board_early_init_f(void)
220 at91_periph_clk_enable(ATMEL_ID_PIOA);
221 at91_periph_clk_enable(ATMEL_ID_PIOB);
222 at91_periph_clk_enable(ATMEL_ID_PIOC);
223 at91_periph_clk_enable(ATMEL_ID_PIOD);
224 at91_periph_clk_enable(ATMEL_ID_PIOE);
226 at91_seriald_hw_init();
233 /* adress of boot parameters */
234 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
236 #ifdef CONFIG_NAND_ATMEL
237 sama5d3xek_nand_hw_init();
239 #ifndef CONFIG_SYS_NO_FLASH
240 sama5d3xek_nor_hw_init();
242 #ifdef CONFIG_CMD_USB
243 sama5d3xek_usb_hw_init();
245 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
248 #ifdef CONFIG_GENERIC_ATMEL_MCI
249 sama5d3xek_mci_hw_init();
251 #ifdef CONFIG_ATMEL_SPI
252 at91_spi0_hw_init(1 << 0);
262 sama5d3xek_lcd_hw_init();
269 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
270 CONFIG_SYS_SDRAM_SIZE);
274 int board_phy_config(struct phy_device *phydev)
276 /* board specific timings for GMAC */
279 ksz9021_phy_extended_write(phydev,
280 MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
283 ksz9021_phy_extended_write(phydev,
284 MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
286 /* rx/tx clock delay */
287 ksz9021_phy_extended_write(phydev,
288 MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
292 /* always run the PHY's config routine */
293 if (phydev->drv->config)
294 return phydev->drv->config(phydev);
299 int board_eth_init(bd_t *bis)
305 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
307 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00);
309 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
310 usba_udc_probe(&pdata);
311 #ifdef CONFIG_USB_ETH_RNDIS
312 usb_eth_initialize(bis);
319 #ifdef CONFIG_GENERIC_ATMEL_MCI
320 int board_mmc_init(bd_t *bis)
324 rc = atmel_mci_init((void *)ATMEL_BASE_MCI0);
330 /* SPI chip select control */
331 #ifdef CONFIG_ATMEL_SPI
334 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
336 return bus == 0 && cs < 4;
339 void spi_cs_activate(struct spi_slave *slave)
343 at91_set_pio_output(AT91_PIO_PORTD, 13, 0);
345 at91_set_pio_output(AT91_PIO_PORTD, 14, 0);
347 at91_set_pio_output(AT91_PIO_PORTD, 15, 0);
349 at91_set_pio_output(AT91_PIO_PORTD, 16, 0);
355 void spi_cs_deactivate(struct spi_slave *slave)
359 at91_set_pio_output(AT91_PIO_PORTD, 13, 1);
361 at91_set_pio_output(AT91_PIO_PORTD, 14, 1);
363 at91_set_pio_output(AT91_PIO_PORTD, 15, 1);
365 at91_set_pio_output(AT91_PIO_PORTD, 16, 1);
370 #endif /* CONFIG_ATMEL_SPI */
372 #ifdef CONFIG_BOARD_LATE_INIT
373 int board_late_init(void)
375 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
376 const int MAX_STR_LEN = 32;
377 char name[MAX_STR_LEN], *p;
380 strncpy(name, get_cpu_name(), MAX_STR_LEN);
381 for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++)
384 strcat(name, "ek.dtb");
385 setenv("dtb_name", name);
392 #ifdef CONFIG_SPL_BUILD
393 void spl_board_init(void)
395 #ifdef CONFIG_SYS_USE_MMC
396 sama5d3xek_mci_hw_init();
397 #elif CONFIG_SYS_USE_NANDFLASH
398 sama5d3xek_nand_hw_init();
399 #elif CONFIG_SYS_USE_SERIALFLASH
400 at91_spi0_hw_init(1 << 0);
404 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
406 ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
408 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
409 ATMEL_MPDDRC_CR_NR_ROW_14 |
410 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
411 ATMEL_MPDDRC_CR_ENRDM_ON |
412 ATMEL_MPDDRC_CR_NB_8BANKS |
413 ATMEL_MPDDRC_CR_NDQS_DISABLED |
414 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
415 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
417 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
418 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
422 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
423 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
424 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
425 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
426 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
427 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
428 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
429 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
431 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
432 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
433 28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
434 26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
436 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
437 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
438 2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
439 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
440 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
445 struct atmel_mpddrc_config ddr2;
449 /* Enable MPDDR clock */
450 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
451 at91_system_clk_enable(AT91_PMC_DDR);
453 /* DDRAM2 Controller initialize */
454 ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
457 void at91_pmc_init(void)
461 tmp = AT91_PMC_PLLAR_29 |
462 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
463 AT91_PMC_PLLXR_MUL(43) |
464 AT91_PMC_PLLXR_DIV(1);
467 at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
469 tmp = AT91_PMC_MCKR_MDIV_4 |
470 AT91_PMC_MCKR_CSS_PLLA;