1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Microchip Technology, Inc.
4 * Eugen Hristev <eugen.hristev@microchip.com>
8 #include <debug_uart.h>
10 #include <asm/arch/at91_common.h>
11 #include <asm/arch/atmel_pio4.h>
12 #include <asm/arch/atmel_mpddrc.h>
13 #include <asm/arch/atmel_sdhci.h>
14 #include <asm/arch/clk.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/sama5d2.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 int board_late_init(void)
25 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
26 static void board_uart0_hw_init(void)
28 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
29 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
31 at91_periph_clk_enable(ATMEL_ID_UART0);
34 void board_debug_uart_init(void)
36 board_uart0_hw_init();
40 int board_early_init_f(void)
42 #ifdef CONFIG_DEBUG_UART
50 /* address of boot parameters */
51 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
58 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
59 CONFIG_SYS_SDRAM_SIZE);
63 #define MAC24AA_MAC_OFFSET 0xfa
67 #ifdef CONFIG_I2C_EEPROM
68 at91_set_ethaddr(MAC24AA_MAC_OFFSET);
74 #ifdef CONFIG_SPL_BUILD
76 /* must set PB25 low to enable the CAN transceivers */
77 static void board_can_stdby_dis(void)
79 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
82 static void board_leds_init(void)
84 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
85 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
86 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
89 /* deassert reset lines for external periph in case of warm reboot */
90 static void board_reset_additional_periph(void)
92 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
93 atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
94 atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
95 atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
98 static void board_start_additional_periph(void)
100 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
101 atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
102 atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
103 atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
106 #ifdef CONFIG_SD_BOOT
107 void spl_mmc_init(void)
109 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */
110 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */
111 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */
112 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */
113 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */
114 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */
115 atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */
117 at91_periph_clk_enable(ATMEL_ID_SDMMC0);
121 void spl_board_init(void)
123 #ifdef CONFIG_SD_BOOT
126 board_reset_additional_periph();
127 board_can_stdby_dis();
131 void spl_display_print(void)
135 void spl_board_prepare_for_boot(void)
137 board_start_additional_periph();
140 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
142 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
144 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
145 ATMEL_MPDDRC_CR_NR_ROW_14 |
146 ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
147 ATMEL_MPDDRC_CR_DIC_DS |
148 ATMEL_MPDDRC_CR_NB_8BANKS |
149 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
150 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
154 ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
155 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
156 (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
157 (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
158 (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
159 (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
160 (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
161 (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
163 ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
164 (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
165 (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
166 (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
168 ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
169 (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
170 (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
171 (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
172 (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
177 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
178 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
179 struct atmel_mpddrc_config ddrc_config;
182 ddrc_conf(&ddrc_config);
184 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
185 writel(AT91_PMC_DDR, &pmc->scer);
187 reg = readl(&mpddrc->io_calibr);
188 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
189 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
190 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
191 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
192 writel(reg, &mpddrc->io_calibr);
194 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
195 &mpddrc->rd_data_path);
197 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
199 writel(0x5355, &mpddrc->cal_mr4);
200 writel(64, &mpddrc->tim_cal);
203 void at91_pmc_init(void)
208 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
209 * so we need to slow down and configure MCKR accordingly.
210 * This is why we have a special flavor of the switching function.
212 tmp = AT91_PMC_MCKR_PLLADIV_2 |
213 AT91_PMC_MCKR_MDIV_3 |
214 AT91_PMC_MCKR_CSS_MAIN;
215 at91_mck_init_down(tmp);
217 tmp = AT91_PMC_PLLAR_29 |
218 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
219 AT91_PMC_PLLXR_MUL(82) |
220 AT91_PMC_PLLXR_DIV(1);
223 tmp = AT91_PMC_MCKR_H32MXDIV |
224 AT91_PMC_MCKR_PLLADIV_2 |
225 AT91_PMC_MCKR_MDIV_3 |
226 AT91_PMC_MCKR_CSS_PLLA;