2 * Copyright (C) 2010 Atmel Corporation
4 * Copyright (C) 2012 Andreas Bießmann <andreas.devel@googlemail.com>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/sdram.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/hmatrix.h>
18 #include <asm/arch/mmu.h>
19 #include <asm/arch/portmux.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
25 /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */
26 .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
27 .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
28 .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
31 /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */
32 .virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT,
33 .nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT,
34 .phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT)
37 /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */
38 .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
39 .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
40 .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
41 | MMU_VMR_CACHE_WRBACK,
45 static const struct sdram_config sdram_config = {
46 .data_bits = SDRAM_DATA_32BIT,
58 .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
61 int board_early_init_f(void)
63 /* Enable SDRAM in the EBI mux */
64 hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)
65 | HMATRIX_BIT(EBI_NAND_ENABLE));
67 portmux_enable_ebi(32, 23, PORTMUX_EBI_NAND,
69 portmux_select_gpio(PORTMUX_PORT_E, 1 << 23,
70 PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH
73 sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
75 portmux_enable_usart1(PORTMUX_DRIVE_MIN);
77 #if defined(CONFIG_MACB)
78 portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
79 portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
81 #if defined(CONFIG_MMC)
82 portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
84 #if defined(CONFIG_ATMEL_SPI)
85 portmux_enable_spi0(1 << 0, PORTMUX_DRIVE_LOW);
91 int board_early_init_r(void)
93 gd->bd->bi_phy_id[0] = 0x01;
94 gd->bd->bi_phy_id[1] = 0x03;
99 int board_eth_init(bd_t *bi)
101 macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
102 macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
107 /* SPI chip select control */
108 #ifdef CONFIG_ATMEL_SPI
109 #define ATNGW100_DATAFLASH_CS_PIN GPIO_PIN_PA(3)
111 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
113 return bus == 0 && cs == 0;
116 void spi_cs_activate(struct spi_slave *slave)
118 gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 0);
121 void spi_cs_deactivate(struct spi_slave *slave)
123 gpio_set_value(ATNGW100_DATAFLASH_CS_PIN, 1);
125 #endif /* CONFIG_ATMEL_SPI */