2 * Copyright (C) 2012 Atmel Corporation
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/at91sam9x5_matrix.h>
10 #include <asm/arch/at91sam9_smc.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/at91_rstc.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/gpio.h>
15 #include <debug_uart.h>
16 #include <asm/mach-types.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 /* ------------------------------------------------------------------------- */
22 * Miscelaneous platform dependent initialisations
24 #ifdef CONFIG_CMD_NAND
25 static void at91sam9x5ek_nand_hw_init(void)
27 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
28 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
32 csa = readl(&matrix->ebicsa);
33 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
34 /* NAND flash on D16 */
35 csa |= AT91_MATRIX_NFD0_ON_D16;
37 /* Configure IO drive */
38 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
40 writel(csa, &matrix->ebicsa);
42 /* Configure SMC CS3 for NAND/SmartMedia */
43 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
44 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
46 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
47 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
49 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(6),
51 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
52 AT91_SMC_MODE_EXNW_DISABLE |
53 #ifdef CONFIG_SYS_NAND_DBW_16
54 AT91_SMC_MODE_DBW_16 |
55 #else /* CONFIG_SYS_NAND_DBW_8 */
58 AT91_SMC_MODE_TDF_CYCLE(1),
61 at91_periph_clk_enable(ATMEL_ID_PIOCD);
63 /* Configure RDY/BSY */
64 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
65 /* Enable NandFlash */
66 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
68 at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
69 at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
70 at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1); /* NAND ALE */
71 at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1); /* NAND CLE */
72 at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
73 at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
74 at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
75 at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
76 at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
77 at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
78 at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
79 at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
83 #ifdef CONFIG_BOARD_LATE_INIT
84 int board_late_init(void)
86 #ifdef CONFIG_DM_VIDEO
87 at91_video_show_board_info();
93 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
94 void board_debug_uart_init(void)
96 at91_seriald_hw_init();
100 #ifdef CONFIG_BOARD_EARLY_INIT_F
101 int board_early_init_f(void)
103 #ifdef CONFIG_DEBUG_UART
112 /* arch number of AT91SAM9X5EK-Board */
113 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9X5EK;
115 /* adress of boot parameters */
116 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
118 #ifdef CONFIG_CMD_NAND
119 at91sam9x5ek_nand_hw_init();
122 #if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI_HCD)
130 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
131 CONFIG_SYS_SDRAM_SIZE);
135 #if defined(CONFIG_SPL_BUILD)
139 void at91_spl_board_init(void)
141 #ifdef CONFIG_SD_BOOT
143 #elif CONFIG_NAND_BOOT
144 at91sam9x5ek_nand_hw_init();
148 #include <asm/arch/atmel_mpddrc.h>
149 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
151 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
153 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
154 ATMEL_MPDDRC_CR_NR_ROW_13 |
155 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
156 ATMEL_MPDDRC_CR_NB_8BANKS |
157 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
161 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
162 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
163 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
164 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
165 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
166 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
167 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
168 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
170 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
171 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
172 19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
173 18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
175 ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
176 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
177 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
178 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
179 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
184 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
185 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
186 struct atmel_mpddrc_config ddr2;
191 /* enable DDR2 clock */
192 writel(AT91_PMC_DDR, &pmc->scer);
194 /* Chip select 1 is for DDR2/SDRAM */
195 csa = readl(&matrix->ebicsa);
196 csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
197 csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
198 csa |= AT91_MATRIX_EBI_DBPD_OFF;
199 csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
200 writel(csa, &matrix->ebicsa);
202 /* DDRAM2 Controller initialize */
203 ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);