board/atmel/at91sam9n12ek/at91sam9n12ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2013 Atmel Corporation
   4  * Josh Wu <josh.wu@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/at91sam9x5_matrix.h>
  10 #include <asm/arch/at91sam9_smc.h>
  11 #include <asm/arch/at91_common.h>
  12 #include <asm/arch/at91_rstc.h>
  13 #include <asm/arch/at91_pio.h>
  14 #include <asm/arch/clk.h>
  15 #include <debug_uart.h>
  16 #include <lcd.h>
  17 #include <atmel_hlcdc.h>
  18 #include <netdev.h>
  19
  20 #ifdef CONFIG_LCD_INFO
  21 #include <nand.h>
  22 #include <version.h>
  23 #endif
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31 #ifdef CONFIG_NAND_ATMEL
  32 static void at91sam9n12ek_nand_hw_init(void)
  33 {
  34         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  35         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  36         unsigned long csa;
  37
  38         /* Assign CS3 to NAND/SmartMedia Interface */
  39         csa = readl(&matrix->ebicsa);
  40         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  41         /* Configure databus */
  42         csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
  43         /* Configure IO drive */
  44         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
  45
  46         writel(csa, &matrix->ebicsa);
  47
  48         /* Configure SMC CS3 for NAND/SmartMedia */
  49         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  50                 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
  51                 &smc->cs[3].setup);
  52         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
  53                 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
  54                 &smc->cs[3].pulse);
  55         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
  56                 &smc->cs[3].cycle);
  57         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  58                 AT91_SMC_MODE_EXNW_DISABLE |
  59 #ifdef CONFIG_SYS_NAND_DBW_16
  60                 AT91_SMC_MODE_DBW_16 |
  61 #else /* CONFIG_SYS_NAND_DBW_8 */
  62                 AT91_SMC_MODE_DBW_8 |
  63 #endif
  64                 AT91_SMC_MODE_TDF_CYCLE(1),
  65                 &smc->cs[3].mode);
  66
  67         /* Configure RDY/BSY pin */
  68         at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
  69
  70         /* Configure ENABLE pin for NandFlash */
  71         at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
  72
  73         at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);    /* NAND OE */
  74         at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);    /* NAND WE */
  75         at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 1);    /* ALE */
  76         at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 1);    /* CLE */
  77 }
  78 #endif
  79
  80 #ifdef CONFIG_LCD
  81 vidinfo_t panel_info = {
  82         .vl_col = 480,
  83         .vl_row = 272,
  84         .vl_clk = 9000000,
  85         .vl_bpix = LCD_BPP,
  86         .vl_sync = 0,
  87         .vl_tft = 1,
  88         .vl_hsync_len = 5,
  89         .vl_left_margin = 8,
  90         .vl_right_margin = 43,
  91         .vl_vsync_len = 10,
  92         .vl_upper_margin = 4,
  93         .vl_lower_margin = 12,
  94         .mmio = ATMEL_BASE_LCDC,
  95 };
  96
  97 void lcd_enable(void)
  98 {
  99         at91_set_pio_output(AT91_PIO_PORTC, 25, 0);     /* power up */
 100 }
 101
 102 void lcd_disable(void)
 103 {
 104         at91_set_pio_output(AT91_PIO_PORTC, 25, 1);     /* power down */
 105 }
 106
 107 #ifdef CONFIG_LCD_INFO
 108 void lcd_show_board_info(void)
 109 {
 110         ulong dram_size, nand_size;
 111         int i;
 112         char temp[32];
 113
 114         lcd_printf("%s\n", U_BOOT_VERSION);
 115         lcd_printf("ATMEL Corp\n");
 116         lcd_printf("at91@atmel.com\n");
 117         lcd_printf("%s CPU at %s MHz\n",
 118                 ATMEL_CPU_NAME,
 119                 strmhz(temp, get_cpu_clk_rate()));
 120
 121         dram_size = 0;
 122         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 123                 dram_size += gd->bd->bi_dram[i].size;
 124         nand_size = 0;
 125         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 126                 nand_size += get_nand_dev_by_index(i)->size;
 127         lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 128                 dram_size >> 20,
 129                 nand_size >> 20);
 130 }
 131 #endif /* CONFIG_LCD_INFO */
 132 #endif /* CONFIG_LCD */
 133
 134 #ifdef CONFIG_KS8851_MLL
 135 void at91sam9n12ek_ks8851_hw_init(void)
 136 {
 137         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
 138
 139         writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
 140                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
 141                &smc->cs[2].setup);
 142         writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
 143                AT91_SMC_PULSE_NRD(7) | AT91_SMC_PULSE_NCS_RD(7),
 144                &smc->cs[2].pulse);
 145         writel(AT91_SMC_CYCLE_NWE(9) | AT91_SMC_CYCLE_NRD(9),
 146                &smc->cs[2].cycle);
 147         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 148                AT91_SMC_MODE_EXNW_DISABLE |
 149                AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
 150                AT91_SMC_MODE_TDF_CYCLE(1),
 151                &smc->cs[2].mode);
 152
 153         /* Configure NCS2 PIN */
 154         at91_pio3_set_b_periph(AT91_PIO_PORTD, 19, 0);
 155 }
 156 #endif
 157
 158 #ifdef CONFIG_USB_ATMEL
 159 void at91sam9n12ek_usb_hw_init(void)
 160 {
 161         at91_set_pio_output(AT91_PIO_PORTB, 7, 0);
 162 }
 163 #endif
 164
 165 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 166 void board_debug_uart_init(void)
 167 {
 168         at91_seriald_hw_init();
 169 }
 170 #endif
 171
 172 #ifdef CONFIG_BOARD_EARLY_INIT_F
 173 int board_early_init_f(void)
 174 {
 175 #ifdef CONFIG_DEBUG_UART
 176         debug_uart_init();
 177 #endif
 178         return 0;
 179 }
 180 #endif
 181
 182 int board_init(void)
 183 {
 184         /* adress of boot parameters */
 185         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 186
 187 #ifdef CONFIG_NAND_ATMEL
 188         at91sam9n12ek_nand_hw_init();
 189 #endif
 190
 191 #ifdef CONFIG_LCD
 192         at91_lcd_hw_init();
 193 #endif
 194
 195 #ifdef CONFIG_KS8851_MLL
 196         at91sam9n12ek_ks8851_hw_init();
 197 #endif
 198
 199 #ifdef CONFIG_USB_ATMEL
 200         at91sam9n12ek_usb_hw_init();
 201 #endif
 202
 203         return 0;
 204 }
 205
 206 #ifdef CONFIG_KS8851_MLL
 207 int board_eth_init(bd_t *bis)
 208 {
 209         return ks8851_mll_initialize(0, CONFIG_KS8851_MLL_BASEADDR);
 210 }
 211 #endif
 212
 213 int dram_init(void)
 214 {
 215         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 216                                         CONFIG_SYS_SDRAM_SIZE);
 217         return 0;
 218 }
 219
 220 #if defined(CONFIG_SPL_BUILD)
 221 #include <spl.h>
 222 #include <nand.h>
 223
 224 void at91_spl_board_init(void)
 225 {
 226 #ifdef CONFIG_SD_BOOT
 227         at91_mci_hw_init();
 228 #elif CONFIG_NAND_BOOT
 229         at91sam9n12ek_nand_hw_init();
 230 #elif CONFIG_SPI_BOOT
 231         at91_spi0_hw_init(1 << 4);
 232 #endif
 233 }
 234
 235 #include <asm/arch/atmel_mpddrc.h>
 236 static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
 237 {
 238         ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
 239
 240         ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 241                     ATMEL_MPDDRC_CR_NR_ROW_13 |
 242                     ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
 243                     ATMEL_MPDDRC_CR_NB_8BANKS |
 244                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED);
 245
 246         ddr2->rtr = 0x411;
 247
 248         ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 249                       2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 250                       2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 251                       8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 252                       2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 253                       2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 254                       2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 255                       2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 256
 257         ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
 258                       200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 259                       19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 260                       18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
 261
 262         ddr2->tpr2 = (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 263                       3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 264                       7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 265                       2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
 266 }
 267
 268 void mem_init(void)
 269 {
 270         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 271         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
 272         struct atmel_mpddrc_config ddr2;
 273         unsigned long csa;
 274
 275         ddr2_conf(&ddr2);
 276
 277         /* enable DDR2 clock */
 278         writel(AT91_PMC_DDR, &pmc->scer);
 279
 280         /* Chip select 1 is for DDR2/SDRAM */
 281         csa = readl(&matrix->ebicsa);
 282         csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
 283         csa &= ~AT91_MATRIX_EBI_DBPU_OFF;
 284         csa |= AT91_MATRIX_EBI_DBPD_OFF;
 285         csa |= AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
 286         writel(csa, &matrix->ebicsa);
 287
 288         /* DDRAM2 Controller initialize */
 289         ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2);
 290 }
 291 #endif