2 * (C) Copyright 2013 Atmel Corporation
3 * Josh Wu <josh.wu@atmel.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91sam9x5_matrix.h>
27 #include <asm/arch/at91sam9_smc.h>
28 #include <asm/arch/at91_common.h>
29 #include <asm/arch/at91_pmc.h>
30 #include <asm/arch/at91_rstc.h>
31 #include <asm/arch/at91_pio.h>
32 #include <asm/arch/clk.h>
34 #include <atmel_hlcdc.h>
35 #include <atmel_mci.h>
37 #ifdef CONFIG_LCD_INFO
42 DECLARE_GLOBAL_DATA_PTR;
44 /* ------------------------------------------------------------------------- */
46 * Miscelaneous platform dependent initialisations
48 #ifdef CONFIG_NAND_ATMEL
49 static void at91sam9n12ek_nand_hw_init(void)
51 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
52 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
55 /* Assign CS3 to NAND/SmartMedia Interface */
56 csa = readl(&matrix->ebicsa);
57 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
58 /* Configure databus */
59 csa &= ~AT91_MATRIX_NFD0_ON_D16; /* nandflash connect to D0~D15 */
60 /* Configure IO drive */
61 csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
63 writel(csa, &matrix->ebicsa);
65 /* Configure SMC CS3 for NAND/SmartMedia */
66 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
67 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
69 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
70 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(6),
72 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(7),
74 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
75 AT91_SMC_MODE_EXNW_DISABLE |
76 #ifdef CONFIG_SYS_NAND_DBW_16
77 AT91_SMC_MODE_DBW_16 |
78 #else /* CONFIG_SYS_NAND_DBW_8 */
81 AT91_SMC_MODE_TDF_CYCLE(1),
84 /* Configure RDY/BSY pin */
85 at91_set_pio_input(AT91_PIO_PORTD, 5, 1);
87 /* Configure ENABLE pin for NandFlash */
88 at91_set_pio_output(AT91_PIO_PORTD, 4, 1);
90 at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
91 at91_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
92 at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* ALE */
93 at91_set_a_periph(AT91_PIO_PORTD, 3, 1); /* CLE */
98 vidinfo_t panel_info = {
107 .vl_right_margin = 43,
109 .vl_upper_margin = 4,
110 .vl_lower_margin = 12,
111 .mmio = ATMEL_BASE_LCDC,
114 void lcd_enable(void)
116 at91_set_pio_output(AT91_PIO_PORTC, 25, 0); /* power up */
119 void lcd_disable(void)
121 at91_set_pio_output(AT91_PIO_PORTC, 25, 1); /* power down */
124 #ifdef CONFIG_LCD_INFO
125 void lcd_show_board_info(void)
127 ulong dram_size, nand_size;
131 lcd_printf("%s\n", U_BOOT_VERSION);
132 lcd_printf("ATMEL Corp\n");
133 lcd_printf("at91@atmel.com\n");
134 lcd_printf("%s CPU at %s MHz\n",
136 strmhz(temp, get_cpu_clk_rate()));
139 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
140 dram_size += gd->bd->bi_dram[i].size;
142 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
143 nand_size += nand_info[i].size;
144 lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
148 #endif /* CONFIG_LCD_INFO */
149 #endif /* CONFIG_LCD */
151 /* SPI chip select control */
152 #ifdef CONFIG_ATMEL_SPI
154 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
156 return bus == 0 && cs < 2;
159 void spi_cs_activate(struct spi_slave *slave)
163 at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
166 at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
171 void spi_cs_deactivate(struct spi_slave *slave)
175 at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
178 at91_set_pio_output(AT91_PIO_PORTA, 7, 1);
182 #endif /* CONFIG_ATMEL_SPI */
184 #ifdef CONFIG_GENERIC_ATMEL_MCI
185 int board_mmc_init(bd_t *bd)
189 return atmel_mci_init((void *)ATMEL_BASE_HSMCI0);
193 int board_early_init_f(void)
195 /* Enable clocks for all PIOs */
196 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
197 writel((1 << ATMEL_ID_PIOAB) | (1 << ATMEL_ID_PIOCD), &pmc->pcer);
199 at91_seriald_hw_init();
205 /* adress of boot parameters */
206 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
208 #ifdef CONFIG_NAND_ATMEL
209 at91sam9n12ek_nand_hw_init();
212 #ifdef CONFIG_ATMEL_SPI
213 at91_spi0_hw_init(1 << 0);
225 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
226 CONFIG_SYS_SDRAM_SIZE);