2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/at91sam9g45_matrix.h>
12 #include <asm/arch/at91sam9_smc.h>
13 #include <asm/arch/at91_common.h>
14 #include <asm/arch/at91_pmc.h>
15 #include <asm/arch/at91_rstc.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/clk.h>
19 #include <atmel_lcdc.h>
20 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
25 DECLARE_GLOBAL_DATA_PTR;
27 /* ------------------------------------------------------------------------- */
29 * Miscelaneous platform dependent initialisations
32 #ifdef CONFIG_CMD_NAND
33 void at91sam9m10g45ek_nand_hw_init(void)
35 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
36 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
37 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
41 csa = readl(&matrix->ebicsa);
42 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
43 writel(csa, &matrix->ebicsa);
45 /* Configure SMC CS3 for NAND/SmartMedia */
46 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
47 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
49 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
50 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
52 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
54 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
55 AT91_SMC_MODE_EXNW_DISABLE |
56 #ifdef CONFIG_SYS_NAND_DBW_16
57 AT91_SMC_MODE_DBW_16 |
58 #else /* CONFIG_SYS_NAND_DBW_8 */
61 AT91_SMC_MODE_TDF_CYCLE(3),
64 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
66 /* Configure RDY/BSY */
67 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
69 /* Enable NandFlash */
70 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
75 static void at91sam9m10g45ek_usb_hw_init(void)
77 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
79 writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
81 at91_set_gpio_output(AT91_PIN_PD1, 0);
82 at91_set_gpio_output(AT91_PIN_PD3, 0);
87 static void at91sam9m10g45ek_macb_hw_init(void)
89 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
90 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
91 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
95 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
99 * RXDV (PA15) => PHY normal mode (not Test mode)
100 * ERX0 (PA12) => PHY ADDR0
101 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
103 * PHY has internal pull-down
105 writel(pin_to_mask(AT91_PIN_PA15) |
106 pin_to_mask(AT91_PIN_PA12) |
107 pin_to_mask(AT91_PIN_PA13),
110 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
112 /* Need to reset PHY -> 500ms reset */
113 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
114 AT91_RSTC_MR_URSTEN, &rstc->mr);
116 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
118 /* Wait for end hardware reset */
119 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
122 /* Restore NRST value */
123 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
126 /* Re-enable pull-up */
127 writel(pin_to_mask(AT91_PIN_PA15) |
128 pin_to_mask(AT91_PIN_PA12) |
129 pin_to_mask(AT91_PIN_PA13),
139 vidinfo_t panel_info = {
143 vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
144 ATMEL_LCDC_INVFRAME_NORMAL,
153 mmio : ATMEL_BASE_LCDC,
157 void lcd_enable(void)
159 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
162 void lcd_disable(void)
164 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
167 static void at91sam9m10g45ek_lcd_hw_init(void)
169 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
171 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
172 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
173 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
174 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
175 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
177 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
178 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
179 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
180 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
181 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
182 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
183 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
184 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
185 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
186 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
187 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
188 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
189 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
190 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
191 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
192 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
193 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
194 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
195 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
196 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
197 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
198 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
199 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
200 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
202 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
204 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
207 #ifdef CONFIG_LCD_INFO
211 void lcd_show_board_info(void)
213 ulong dram_size, nand_size;
217 lcd_printf ("%s\n", U_BOOT_VERSION);
218 lcd_printf ("(C) 2008 ATMEL Corp\n");
219 lcd_printf ("at91support@atmel.com\n");
220 lcd_printf ("%s CPU at %s MHz\n",
222 strmhz(temp, get_cpu_clk_rate()));
225 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
226 dram_size += gd->bd->bi_dram[i].size;
228 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
229 nand_size += nand_info[i].size;
230 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
234 #endif /* CONFIG_LCD_INFO */
237 int board_early_init_f(void)
239 at91_seriald_hw_init();
245 /* arch number of AT91SAM9M10G45EK-Board */
246 #ifdef CONFIG_AT91SAM9M10G45EK
247 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
248 #elif defined CONFIG_AT91SAM9G45EKES
249 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
252 /* adress of boot parameters */
253 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
255 #ifdef CONFIG_CMD_NAND
256 at91sam9m10g45ek_nand_hw_init();
258 #ifdef CONFIG_CMD_USB
259 at91sam9m10g45ek_usb_hw_init();
261 #ifdef CONFIG_HAS_DATAFLASH
262 at91_spi0_hw_init(1 << 0);
264 #ifdef CONFIG_ATMEL_SPI
265 at91_spi0_hw_init(1 << 4);
268 at91sam9m10g45ek_macb_hw_init();
271 at91sam9m10g45ek_lcd_hw_init();
278 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
279 CONFIG_SYS_SDRAM_SIZE);
283 #ifdef CONFIG_RESET_PHY_R
289 int board_eth_init(bd_t *bis)
293 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
298 /* SPI chip select control */
299 #ifdef CONFIG_ATMEL_SPI
302 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
304 return bus == 0 && cs < 2;
307 void spi_cs_activate(struct spi_slave *slave)
311 at91_set_gpio_output(AT91_PIN_PB18, 0);
315 at91_set_gpio_output(AT91_PIN_PB3, 0);
320 void spi_cs_deactivate(struct spi_slave *slave)
324 at91_set_gpio_output(AT91_PIN_PB18, 1);
328 at91_set_gpio_output(AT91_PIN_PB3, 1);
332 #endif /* CONFIG_ATMEL_SPI */