2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/clk.h>
12 #include <asm/arch/at91sam9g45_matrix.h>
13 #include <asm/arch/at91sam9_smc.h>
14 #include <asm/arch/at91_common.h>
15 #include <asm/arch/at91_pmc.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/clk.h>
19 #include <linux/mtd/nand.h>
20 #include <atmel_lcdc.h>
21 #include <atmel_mci.h>
22 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
27 DECLARE_GLOBAL_DATA_PTR;
29 /* ------------------------------------------------------------------------- */
31 * Miscelaneous platform dependent initialisations
34 #ifdef CONFIG_CMD_NAND
35 void at91sam9m10g45ek_nand_hw_init(void)
37 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
38 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
39 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
43 csa = readl(&matrix->ebicsa);
44 csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
45 writel(csa, &matrix->ebicsa);
47 /* Configure SMC CS3 for NAND/SmartMedia */
48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
51 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
54 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
56 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
57 AT91_SMC_MODE_EXNW_DISABLE |
58 #ifdef CONFIG_SYS_NAND_DBW_16
59 AT91_SMC_MODE_DBW_16 |
60 #else /* CONFIG_SYS_NAND_DBW_8 */
63 AT91_SMC_MODE_TDF_CYCLE(3),
66 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
68 /* Configure RDY/BSY */
69 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
71 /* Enable NandFlash */
72 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
76 #if defined(CONFIG_SPL_BUILD)
80 void at91_spl_board_init(void)
83 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
84 * test mode, so it needs do some action to exit test mode.
86 at91_periph_clk_enable(ATMEL_ID_PIODE);
87 at91_set_gpio_output(AT91_PIN_PD7, 0);
88 at91_set_gpio_output(AT91_PIN_PD8, 0);
89 at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
90 at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
92 #ifdef CONFIG_SYS_USE_MMC
94 #elif CONFIG_SYS_USE_NANDFLASH
95 at91sam9m10g45ek_nand_hw_init();
99 #include <asm/arch/atmel_mpddrc.h>
100 static void ddr2_conf(struct atmel_mpddr *ddr2)
102 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
104 ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
105 ATMEL_MPDDRC_CR_NR_ROW_14 |
106 ATMEL_MPDDRC_CR_DQMS_SHARED |
107 ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
111 ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
112 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
113 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
114 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
115 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
116 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
117 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
118 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
120 ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
121 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
122 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
123 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
125 ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
126 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
127 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
128 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
133 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
134 struct atmel_mpddr ddr2;
138 /* enable DDR2 clock */
139 writel(AT91_PMC_DDR, &pmc->scer);
141 /* DDRAM2 Controller initialize */
142 ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
146 #ifdef CONFIG_CMD_USB
147 static void at91sam9m10g45ek_usb_hw_init(void)
149 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
151 writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
153 at91_set_gpio_output(AT91_PIN_PD1, 0);
154 at91_set_gpio_output(AT91_PIN_PD3, 0);
159 static void at91sam9m10g45ek_macb_hw_init(void)
161 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
162 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
165 writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
168 * Disable pull-up on:
169 * RXDV (PA15) => PHY normal mode (not Test mode)
170 * ERX0 (PA12) => PHY ADDR0
171 * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
173 * PHY has internal pull-down
175 writel(pin_to_mask(AT91_PIN_PA15) |
176 pin_to_mask(AT91_PIN_PA12) |
177 pin_to_mask(AT91_PIN_PA13),
182 /* Re-enable pull-up */
183 writel(pin_to_mask(AT91_PIN_PA15) |
184 pin_to_mask(AT91_PIN_PA12) |
185 pin_to_mask(AT91_PIN_PA13),
195 vidinfo_t panel_info = {
199 .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
200 ATMEL_LCDC_INVFRAME_NORMAL,
205 .vl_right_margin = 1,
207 .vl_upper_margin = 40,
208 .vl_lower_margin = 1,
209 .mmio = ATMEL_BASE_LCDC,
213 void lcd_enable(void)
215 at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
218 void lcd_disable(void)
220 at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
223 static void at91sam9m10g45ek_lcd_hw_init(void)
225 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
227 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
228 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
229 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
230 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
231 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
233 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
234 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
235 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
236 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
237 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
238 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
239 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
240 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
241 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
242 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
243 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
244 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
245 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
246 at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
247 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
248 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
249 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
250 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
251 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
252 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
253 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
254 at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
255 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
256 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
258 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
260 gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
263 #ifdef CONFIG_LCD_INFO
267 void lcd_show_board_info(void)
269 ulong dram_size, nand_size;
273 lcd_printf ("%s\n", U_BOOT_VERSION);
274 lcd_printf ("(C) 2008 ATMEL Corp\n");
275 lcd_printf ("at91support@atmel.com\n");
276 lcd_printf ("%s CPU at %s MHz\n",
278 strmhz(temp, get_cpu_clk_rate()));
281 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
282 dram_size += gd->bd->bi_dram[i].size;
284 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
285 nand_size += nand_info[i].size;
286 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
290 #endif /* CONFIG_LCD_INFO */
293 #ifdef CONFIG_GENERIC_ATMEL_MCI
294 int board_mmc_init(bd_t *bis)
298 return atmel_mci_init((void *)ATMEL_BASE_MCI0);
302 int board_early_init_f(void)
304 at91_seriald_hw_init();
310 /* arch number of AT91SAM9M10G45EK-Board */
311 #ifdef CONFIG_AT91SAM9M10G45EK
312 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
313 #elif defined CONFIG_AT91SAM9G45EKES
314 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
317 /* adress of boot parameters */
318 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
320 #ifdef CONFIG_CMD_NAND
321 at91sam9m10g45ek_nand_hw_init();
323 #ifdef CONFIG_CMD_USB
324 at91sam9m10g45ek_usb_hw_init();
326 #ifdef CONFIG_HAS_DATAFLASH
327 at91_spi0_hw_init(1 << 0);
329 #ifdef CONFIG_ATMEL_SPI
330 at91_spi0_hw_init(1 << 4);
333 at91sam9m10g45ek_macb_hw_init();
336 at91sam9m10g45ek_lcd_hw_init();
343 gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
344 CONFIG_SYS_SDRAM_SIZE);
348 #ifdef CONFIG_RESET_PHY_R
354 int board_eth_init(bd_t *bis)
358 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
363 /* SPI chip select control */
364 #ifdef CONFIG_ATMEL_SPI
367 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
369 return bus == 0 && cs < 2;
372 void spi_cs_activate(struct spi_slave *slave)
376 at91_set_gpio_output(AT91_PIN_PB18, 0);
380 at91_set_gpio_output(AT91_PIN_PB3, 0);
385 void spi_cs_deactivate(struct spi_slave *slave)
389 at91_set_gpio_output(AT91_PIN_PB18, 1);
393 at91_set_gpio_output(AT91_PIN_PB3, 1);
397 #endif /* CONFIG_ATMEL_SPI */