Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
[oweals/u-boot.git] / board / atmel / at91sam9263ek / at91sam9263ek.c
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian.pop@leadtechdesign.com>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #include <common.h>
26 #include <asm/sizes.h>
27 #include <asm/arch/at91sam9263.h>
28 #include <asm/arch/at91sam9263_matrix.h>
29 #include <asm/arch/at91sam9_smc.h>
30 #include <asm/arch/at91_common.h>
31 #include <asm/arch/at91_pmc.h>
32 #include <asm/arch/at91_rstc.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/io.h>
35 #include <asm/arch/hardware.h>
36 #include <lcd.h>
37 #include <atmel_lcdc.h>
38 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39 #include <net.h>
40 #endif
41 #include <netdev.h>
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45 /* ------------------------------------------------------------------------- */
46 /*
47  * Miscelaneous platform dependent initialisations
48  */
49
50 #ifdef CONFIG_CMD_NAND
51 static void at91sam9263ek_nand_hw_init(void)
52 {
53         unsigned long csa;
54
55         /* Enable CS3 */
56         csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
57         at91_sys_write(AT91_MATRIX_EBI0CSA,
58                        csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
59
60         /* Configure SMC CS3 for NAND/SmartMedia */
61         at91_sys_write(AT91_SMC_SETUP(3),
62                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
63                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
64         at91_sys_write(AT91_SMC_PULSE(3),
65                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
66                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
67         at91_sys_write(AT91_SMC_CYCLE(3),
68                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
69         at91_sys_write(AT91_SMC_MODE(3),
70                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
71                        AT91_SMC_EXNWMODE_DISABLE |
72 #ifdef CONFIG_SYS_NAND_DBW_16
73                        AT91_SMC_DBW_16 |
74 #else /* CONFIG_SYS_NAND_DBW_8 */
75                        AT91_SMC_DBW_8 |
76 #endif
77                        AT91_SMC_TDF_(2));
78
79         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
80                                       1 << AT91SAM9263_ID_PIOCDE);
81
82         /* Configure RDY/BSY */
83         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
84
85         /* Enable NandFlash */
86         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
87 }
88 #endif
89
90 #ifdef CONFIG_MACB
91 static void at91sam9263ek_macb_hw_init(void)
92 {
93         /* Enable clock */
94         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
95
96         /*
97          * Disable pull-up on:
98          *      RXDV (PC25) => PHY normal mode (not Test mode)
99          *      ERX0 (PE25) => PHY ADDR0
100          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
101          *
102          * PHY has internal pull-down
103          */
104         writel(pin_to_mask(AT91_PIN_PC25),
105                pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
106         writel(pin_to_mask(AT91_PIN_PE25) |
107                pin_to_mask(AT91_PIN_PE26),
108                pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
109
110         /* Need to reset PHY -> 500ms reset */
111         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
112                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
113                                      AT91_RSTC_URSTEN);
114
115         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
116
117         /* Wait for end hardware reset */
118         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
119
120         /* Restore NRST value */
121         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
122                                      (AT91_RSTC_ERSTL & (0x0 << 8)) |
123                                      AT91_RSTC_URSTEN);
124
125         /* Re-enable pull-up */
126         writel(pin_to_mask(AT91_PIN_PC25),
127                pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
128         writel(pin_to_mask(AT91_PIN_PE25) |
129                pin_to_mask(AT91_PIN_PE26),
130                pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
131
132         at91_macb_hw_init();
133 }
134 #endif
135
136 #ifdef CONFIG_LCD
137 vidinfo_t panel_info = {
138         vl_col:         240,
139         vl_row:         320,
140         vl_clk:         4965000,
141         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
142                         ATMEL_LCDC_INVFRAME_INVERTED,
143         vl_bpix:        3,
144         vl_tft:         1,
145         vl_hsync_len:   5,
146         vl_left_margin: 1,
147         vl_right_margin:33,
148         vl_vsync_len:   1,
149         vl_upper_margin:1,
150         vl_lower_margin:0,
151         mmio:           AT91SAM9263_LCDC_BASE,
152 };
153
154 void lcd_enable(void)
155 {
156         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
157 }
158
159 void lcd_disable(void)
160 {
161         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
162 }
163
164 static void at91sam9263ek_lcd_hw_init(void)
165 {
166         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
167         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
168         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
169         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
170         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
171         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
172         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
173         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
174         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
175         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
176         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
177         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
178         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
179         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
180         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
181         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
182         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
183         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
184         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
185         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
186         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
187         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
188
189         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
190
191         gd->fb_base = AT91SAM9263_SRAM0_BASE;
192 }
193
194 #ifdef CONFIG_LCD_INFO
195 #include <nand.h>
196 #include <version.h>
197
198 void lcd_show_board_info(void)
199 {
200         ulong dram_size, nand_size;
201         int i;
202         char temp[32];
203
204         lcd_printf ("%s\n", U_BOOT_VERSION);
205         lcd_printf ("(C) 2008 ATMEL Corp\n");
206         lcd_printf ("at91support@atmel.com\n");
207         lcd_printf ("%s CPU at %s MHz\n",
208                 AT91_CPU_NAME,
209                 strmhz(temp, AT91_CPU_CLOCK));
210
211         dram_size = 0;
212         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
213                 dram_size += gd->bd->bi_dram[i].size;
214         nand_size = 0;
215         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
216                 nand_size += nand_info[i].size;
217         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
218                 dram_size >> 20,
219                 nand_size >> 20 );
220 }
221 #endif /* CONFIG_LCD_INFO */
222 #endif
223
224 int board_init(void)
225 {
226         /* Enable Ctrlc */
227         console_init_f();
228
229         /* arch number of AT91SAM9263EK-Board */
230         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
231         /* adress of boot parameters */
232         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
233
234         at91_serial_hw_init();
235 #ifdef CONFIG_CMD_NAND
236         at91sam9263ek_nand_hw_init();
237 #endif
238 #ifdef CONFIG_HAS_DATAFLASH
239         at91_set_gpio_output(AT91_PIN_PE20, 1); /* select spi0 clock */
240         at91_spi0_hw_init(1 << 0);
241 #endif
242 #ifdef CONFIG_MACB
243         at91sam9263ek_macb_hw_init();
244 #endif
245 #ifdef CONFIG_USB_OHCI_NEW
246         at91_uhp_hw_init();
247 #endif
248 #ifdef CONFIG_LCD
249         at91sam9263ek_lcd_hw_init();
250 #endif
251         return 0;
252 }
253
254 int dram_init(void)
255 {
256         gd->bd->bi_dram[0].start = PHYS_SDRAM;
257         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
258         return 0;
259 }
260
261 #ifdef CONFIG_RESET_PHY_R
262 void reset_phy(void)
263 {
264 #ifdef CONFIG_MACB
265         /*
266          * Initialize ethernet HW addr prior to starting Linux,
267          * needed for nfsroot
268          */
269         eth_init(gd->bd);
270 #endif
271 }
272 #endif
273
274 int board_eth_init(bd_t *bis)
275 {
276         int rc = 0;
277 #ifdef CONFIG_MACB
278         rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
279 #endif
280         return rc;
281 }