board/atmel/at91sam9263ek/at91sam9263ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/sizes.h>
  27 #include <asm/arch/at91sam9263.h>
  28 #include <asm/arch/at91sam9263_matrix.h>
  29 #include <asm/arch/at91sam9_smc.h>
  30 #include <asm/arch/at91_pmc.h>
  31 #include <asm/arch/at91_rstc.h>
  32 #include <asm/arch/gpio.h>
  33 #include <asm/arch/io.h>
  34 #include <lcd.h>
  35 #include <atmel_lcdc.h>
  36 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  37 #include <net.h>
  38 #endif
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 /* ------------------------------------------------------------------------- */
  43 /*
  44  * Miscelaneous platform dependent initialisations
  45  */
  46
  47 static void at91sam9263ek_serial_hw_init(void)
  48 {
  49 #ifdef CONFIG_USART0
  50         at91_set_A_periph(AT91_PIN_PA26, 1);            /* TXD0 */
  51         at91_set_A_periph(AT91_PIN_PA27, 0);            /* RXD0 */
  52         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
  53 #endif
  54
  55 #ifdef CONFIG_USART1
  56         at91_set_A_periph(AT91_PIN_PD0, 1);             /* TXD1 */
  57         at91_set_A_periph(AT91_PIN_PD1, 0);             /* RXD1 */
  58         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
  59 #endif
  60
  61 #ifdef CONFIG_USART2
  62         at91_set_A_periph(AT91_PIN_PD2, 1);             /* TXD2 */
  63         at91_set_A_periph(AT91_PIN_PD3, 0);             /* RXD2 */
  64         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
  65 #endif
  66
  67 #ifdef CONFIG_USART3    /* DBGU */
  68         at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
  69         at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
  70         at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  71 #endif
  72 }
  73
  74 #ifdef CONFIG_CMD_NAND
  75 static void at91sam9263ek_nand_hw_init(void)
  76 {
  77         unsigned long csa;
  78
  79         /* Enable CS3 */
  80         csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
  81         at91_sys_write(AT91_MATRIX_EBI0CSA,
  82                        csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
  83
  84         /* Configure SMC CS3 for NAND/SmartMedia */
  85         at91_sys_write(AT91_SMC_SETUP(3),
  86                        AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
  87                        AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  88         at91_sys_write(AT91_SMC_PULSE(3),
  89                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  90                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  91         at91_sys_write(AT91_SMC_CYCLE(3),
  92                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  93         at91_sys_write(AT91_SMC_MODE(3),
  94                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  95                        AT91_SMC_EXNWMODE_DISABLE |
  96 #ifdef CFG_NAND_DBW_16
  97                        AT91_SMC_DBW_16 |
  98 #else /* CFG_NAND_DBW_8 */
  99                        AT91_SMC_DBW_8 |
 100 #endif
 101                        AT91_SMC_TDF_(2));
 102
 103         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
 104                                       1 << AT91SAM9263_ID_PIOCDE);
 105
 106         /* Configure RDY/BSY */
 107         at91_set_gpio_input(AT91_PIN_PA22, 1);
 108
 109         /* Enable NandFlash */
 110         at91_set_gpio_output(AT91_PIN_PD15, 1);
 111 }
 112 #endif
 113
 114 #ifdef CONFIG_HAS_DATAFLASH
 115 static void at91sam9263ek_spi_hw_init(void)
 116 {
 117         at91_set_B_periph(AT91_PIN_PA5, 0);     /* SPI0_NPCS0 */
 118
 119         at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 120         at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 121         at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 122
 123         /* Enable clock */
 124         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
 125 }
 126 #endif
 127
 128 #ifdef CONFIG_MACB
 129 static void at91sam9263ek_macb_hw_init(void)
 130 {
 131         /* Enable clock */
 132         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
 133
 134         /*
 135          * Disable pull-up on:
 136          *      RXDV (PC25) => PHY normal mode (not Test mode)
 137          *      ERX0 (PE25) => PHY ADDR0
 138          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
 139          *
 140          * PHY has internal pull-down
 141          */
 142         writel(pin_to_mask(AT91_PIN_PC25),
 143                pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
 144         writel(pin_to_mask(AT91_PIN_PE25) |
 145                pin_to_mask(AT91_PIN_PE26),
 146                pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
 147
 148         /* Need to reset PHY -> 500ms reset */
 149         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 150                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
 151                                      AT91_RSTC_URSTEN);
 152
 153         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 154
 155         /* Wait for end hardware reset */
 156         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 157
 158         /* Restore NRST value */
 159         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 160                                      (AT91_RSTC_ERSTL & (0x0 << 8)) |
 161                                      AT91_RSTC_URSTEN);
 162
 163         /* Re-enable pull-up */
 164         writel(pin_to_mask(AT91_PIN_PC25),
 165                pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
 166         writel(pin_to_mask(AT91_PIN_PE25) |
 167                pin_to_mask(AT91_PIN_PE26),
 168                pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
 169
 170         at91_set_A_periph(AT91_PIN_PE21, 0);    /* ETXCK_EREFCK */
 171         at91_set_B_periph(AT91_PIN_PC25, 0);    /* ERXDV */
 172         at91_set_A_periph(AT91_PIN_PE25, 0);    /* ERX0 */
 173         at91_set_A_periph(AT91_PIN_PE26, 0);    /* ERX1 */
 174         at91_set_A_periph(AT91_PIN_PE27, 0);    /* ERXER */
 175         at91_set_A_periph(AT91_PIN_PE28, 0);    /* ETXEN */
 176         at91_set_A_periph(AT91_PIN_PE23, 0);    /* ETX0 */
 177         at91_set_A_periph(AT91_PIN_PE24, 0);    /* ETX1 */
 178         at91_set_A_periph(AT91_PIN_PE30, 0);    /* EMDIO */
 179         at91_set_A_periph(AT91_PIN_PE29, 0);    /* EMDC */
 180
 181 #ifndef CONFIG_RMII
 182         at91_set_A_periph(AT91_PIN_PE22, 0);    /* ECRS */
 183         at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
 184         at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
 185         at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
 186         at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
 187         at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
 188         at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
 189         at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
 190 #endif
 191
 192 }
 193 #endif
 194
 195 #ifdef CONFIG_USB_OHCI_NEW
 196 static void at91sam9263ek_uhp_hw_init(void)
 197 {
 198         /* Enable VBus on UHP ports */
 199         at91_set_gpio_output(AT91_PIN_PA21, 0);
 200         at91_set_gpio_output(AT91_PIN_PA24, 0);
 201 }
 202 #endif
 203
 204 #ifdef CONFIG_LCD
 205 vidinfo_t panel_info = {
 206         vl_col:         240,
 207         vl_row:         320,
 208         vl_clk:         4965000,
 209         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 210                         ATMEL_LCDC_INVFRAME_INVERTED,
 211         vl_bpix:        3,
 212         vl_tft:         1,
 213         vl_hsync_len:   5,
 214         vl_left_margin: 1,
 215         vl_right_margin:33,
 216         vl_vsync_len:   1,
 217         vl_upper_margin:1,
 218         vl_lower_margin:0,
 219         mmio:           AT91SAM9263_LCDC_BASE,
 220 };
 221
 222 void lcd_enable(void)
 223 {
 224         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
 225 }
 226
 227 void lcd_disable(void)
 228 {
 229         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
 230 }
 231
 232 static void at91sam9263ek_lcd_hw_init(void)
 233 {
 234         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 235         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 236         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 237         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 238         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 239         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 240         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 241         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 242         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 243         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 244         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 245         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 246         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 247         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
 248         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 249         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 250         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 251         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 252         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 253         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
 254         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 255         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 256
 257         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
 258
 259         gd->fb_base = AT91SAM9263_SRAM0_BASE;
 260 }
 261 #endif
 262
 263 int board_init(void)
 264 {
 265         /* Enable Ctrlc */
 266         console_init_f();
 267
 268         /* arch number of AT91SAM9263EK-Board */
 269         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 270         /* adress of boot parameters */
 271         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 272
 273         at91sam9263ek_serial_hw_init();
 274 #ifdef CONFIG_CMD_NAND
 275         at91sam9263ek_nand_hw_init();
 276 #endif
 277 #ifdef CONFIG_HAS_DATAFLASH
 278         at91sam9263ek_spi_hw_init();
 279 #endif
 280 #ifdef CONFIG_MACB
 281         at91sam9263ek_macb_hw_init();
 282 #endif
 283 #ifdef CONFIG_USB_OHCI_NEW
 284         at91sam9263ek_uhp_hw_init();
 285 #endif
 286 #ifdef CONFIG_LCD
 287         at91sam9263ek_lcd_hw_init();
 288 #endif
 289         return 0;
 290 }
 291
 292 int dram_init(void)
 293 {
 294         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 295         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 296         return 0;
 297 }
 298
 299 #ifdef CONFIG_RESET_PHY_R
 300 void reset_phy(void)
 301 {
 302 #ifdef CONFIG_MACB
 303         /*
 304          * Initialize ethernet HW addr prior to starting Linux,
 305          * needed for nfsroot
 306          */
 307         eth_init(gd->bd);
 308 #endif
 309 }
 310 #endif