at91sam9/at91cap: move common serial initialisation to cpu
[oweals/u-boot.git] / board / atmel / at91sam9263ek / at91sam9263ek.c
1 /*
2  * (C) Copyright 2007-2008
3  * Stelian Pop <stelian.pop@leadtechdesign.com>
4  * Lead Tech Design <www.leadtechdesign.com>
5  *
6  * See file CREDITS for list of people who contributed to this
7  * project.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License as
11  * published by the Free Software Foundation; either version 2 of
12  * the License, or (at your option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22  * MA 02111-1307 USA
23  */
24
25 #include <common.h>
26 #include <asm/sizes.h>
27 #include <asm/arch/at91sam9263.h>
28 #include <asm/arch/at91sam9263_matrix.h>
29 #include <asm/arch/at91sam9_smc.h>
30 #include <asm/arch/at91_common.h>
31 #include <asm/arch/at91_pmc.h>
32 #include <asm/arch/at91_rstc.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/io.h>
35 #include <asm/arch/hardware.h>
36 #include <lcd.h>
37 #include <atmel_lcdc.h>
38 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
39 #include <net.h>
40 #endif
41 #include <netdev.h>
42
43 DECLARE_GLOBAL_DATA_PTR;
44
45 /* ------------------------------------------------------------------------- */
46 /*
47  * Miscelaneous platform dependent initialisations
48  */
49
50 #ifdef CONFIG_CMD_NAND
51 static void at91sam9263ek_nand_hw_init(void)
52 {
53         unsigned long csa;
54
55         /* Enable CS3 */
56         csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
57         at91_sys_write(AT91_MATRIX_EBI0CSA,
58                        csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
59
60         /* Configure SMC CS3 for NAND/SmartMedia */
61         at91_sys_write(AT91_SMC_SETUP(3),
62                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
63                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
64         at91_sys_write(AT91_SMC_PULSE(3),
65                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
66                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
67         at91_sys_write(AT91_SMC_CYCLE(3),
68                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
69         at91_sys_write(AT91_SMC_MODE(3),
70                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
71                        AT91_SMC_EXNWMODE_DISABLE |
72 #ifdef CONFIG_SYS_NAND_DBW_16
73                        AT91_SMC_DBW_16 |
74 #else /* CONFIG_SYS_NAND_DBW_8 */
75                        AT91_SMC_DBW_8 |
76 #endif
77                        AT91_SMC_TDF_(2));
78
79         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
80                                       1 << AT91SAM9263_ID_PIOCDE);
81
82         /* Configure RDY/BSY */
83         at91_set_gpio_input(AT91_PIN_PA22, 1);
84
85         /* Enable NandFlash */
86         at91_set_gpio_output(AT91_PIN_PD15, 1);
87 }
88 #endif
89
90 #ifdef CONFIG_HAS_DATAFLASH
91 static void at91sam9263ek_spi_hw_init(void)
92 {
93         at91_set_B_periph(AT91_PIN_PA5, 0);     /* SPI0_NPCS0 */
94
95         at91_set_B_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
96         at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
97         at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
98
99         /* Enable clock */
100         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
101 }
102 #endif
103
104 #ifdef CONFIG_MACB
105 static void at91sam9263ek_macb_hw_init(void)
106 {
107         /* Enable clock */
108         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
109
110         /*
111          * Disable pull-up on:
112          *      RXDV (PC25) => PHY normal mode (not Test mode)
113          *      ERX0 (PE25) => PHY ADDR0
114          *      ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
115          *
116          * PHY has internal pull-down
117          */
118         writel(pin_to_mask(AT91_PIN_PC25),
119                pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
120         writel(pin_to_mask(AT91_PIN_PE25) |
121                pin_to_mask(AT91_PIN_PE26),
122                pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
123
124         /* Need to reset PHY -> 500ms reset */
125         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
126                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
127                                      AT91_RSTC_URSTEN);
128
129         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
130
131         /* Wait for end hardware reset */
132         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
133
134         /* Restore NRST value */
135         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
136                                      (AT91_RSTC_ERSTL & (0x0 << 8)) |
137                                      AT91_RSTC_URSTEN);
138
139         /* Re-enable pull-up */
140         writel(pin_to_mask(AT91_PIN_PC25),
141                pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
142         writel(pin_to_mask(AT91_PIN_PE25) |
143                pin_to_mask(AT91_PIN_PE26),
144                pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
145
146         at91_set_A_periph(AT91_PIN_PE21, 0);    /* ETXCK_EREFCK */
147         at91_set_B_periph(AT91_PIN_PC25, 0);    /* ERXDV */
148         at91_set_A_periph(AT91_PIN_PE25, 0);    /* ERX0 */
149         at91_set_A_periph(AT91_PIN_PE26, 0);    /* ERX1 */
150         at91_set_A_periph(AT91_PIN_PE27, 0);    /* ERXER */
151         at91_set_A_periph(AT91_PIN_PE28, 0);    /* ETXEN */
152         at91_set_A_periph(AT91_PIN_PE23, 0);    /* ETX0 */
153         at91_set_A_periph(AT91_PIN_PE24, 0);    /* ETX1 */
154         at91_set_A_periph(AT91_PIN_PE30, 0);    /* EMDIO */
155         at91_set_A_periph(AT91_PIN_PE29, 0);    /* EMDC */
156
157 #ifndef CONFIG_RMII
158         at91_set_A_periph(AT91_PIN_PE22, 0);    /* ECRS */
159         at91_set_B_periph(AT91_PIN_PC26, 0);    /* ECOL */
160         at91_set_B_periph(AT91_PIN_PC22, 0);    /* ERX2 */
161         at91_set_B_periph(AT91_PIN_PC23, 0);    /* ERX3 */
162         at91_set_B_periph(AT91_PIN_PC27, 0);    /* ERXCK */
163         at91_set_B_periph(AT91_PIN_PC20, 0);    /* ETX2 */
164         at91_set_B_periph(AT91_PIN_PC21, 0);    /* ETX3 */
165         at91_set_B_periph(AT91_PIN_PC24, 0);    /* ETXER */
166 #endif
167
168 }
169 #endif
170
171 #ifdef CONFIG_USB_OHCI_NEW
172 static void at91sam9263ek_uhp_hw_init(void)
173 {
174         /* Enable VBus on UHP ports */
175         at91_set_gpio_output(AT91_PIN_PA21, 0);
176         at91_set_gpio_output(AT91_PIN_PA24, 0);
177 }
178 #endif
179
180 #ifdef CONFIG_LCD
181 vidinfo_t panel_info = {
182         vl_col:         240,
183         vl_row:         320,
184         vl_clk:         4965000,
185         vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
186                         ATMEL_LCDC_INVFRAME_INVERTED,
187         vl_bpix:        3,
188         vl_tft:         1,
189         vl_hsync_len:   5,
190         vl_left_margin: 1,
191         vl_right_margin:33,
192         vl_vsync_len:   1,
193         vl_upper_margin:1,
194         vl_lower_margin:0,
195         mmio:           AT91SAM9263_LCDC_BASE,
196 };
197
198 void lcd_enable(void)
199 {
200         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power up */
201 }
202
203 void lcd_disable(void)
204 {
205         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power down */
206 }
207
208 static void at91sam9263ek_lcd_hw_init(void)
209 {
210         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
211         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
212         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
213         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
214         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
215         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
216         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
217         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
218         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
219         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
220         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
221         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
222         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
223         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
224         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
225         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
226         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
227         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
228         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
229         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
230         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
231         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
232
233         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
234
235         gd->fb_base = AT91SAM9263_SRAM0_BASE;
236 }
237
238 #ifdef CONFIG_LCD_INFO
239 #include <nand.h>
240 #include <version.h>
241
242 void lcd_show_board_info(void)
243 {
244         ulong dram_size, nand_size;
245         int i;
246         char temp[32];
247
248         lcd_printf ("%s\n", U_BOOT_VERSION);
249         lcd_printf ("(C) 2008 ATMEL Corp\n");
250         lcd_printf ("at91support@atmel.com\n");
251         lcd_printf ("%s CPU at %s MHz\n",
252                 AT91_CPU_NAME,
253                 strmhz(temp, AT91_CPU_CLOCK));
254
255         dram_size = 0;
256         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
257                 dram_size += gd->bd->bi_dram[i].size;
258         nand_size = 0;
259         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
260                 nand_size += nand_info[i].size;
261         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
262                 dram_size >> 20,
263                 nand_size >> 20 );
264 }
265 #endif /* CONFIG_LCD_INFO */
266 #endif
267
268 int board_init(void)
269 {
270         /* Enable Ctrlc */
271         console_init_f();
272
273         /* arch number of AT91SAM9263EK-Board */
274         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
275         /* adress of boot parameters */
276         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
277
278         at91_serial_hw_init();
279 #ifdef CONFIG_CMD_NAND
280         at91sam9263ek_nand_hw_init();
281 #endif
282 #ifdef CONFIG_HAS_DATAFLASH
283         at91sam9263ek_spi_hw_init();
284 #endif
285 #ifdef CONFIG_MACB
286         at91sam9263ek_macb_hw_init();
287 #endif
288 #ifdef CONFIG_USB_OHCI_NEW
289         at91sam9263ek_uhp_hw_init();
290 #endif
291 #ifdef CONFIG_LCD
292         at91sam9263ek_lcd_hw_init();
293 #endif
294         return 0;
295 }
296
297 int dram_init(void)
298 {
299         gd->bd->bi_dram[0].start = PHYS_SDRAM;
300         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
301         return 0;
302 }
303
304 #ifdef CONFIG_RESET_PHY_R
305 void reset_phy(void)
306 {
307 #ifdef CONFIG_MACB
308         /*
309          * Initialize ethernet HW addr prior to starting Linux,
310          * needed for nfsroot
311          */
312         eth_init(gd->bd);
313 #endif
314 }
315 #endif
316
317 int board_eth_init(bd_t *bis)
318 {
319         int rc = 0;
320 #ifdef CONFIG_MACB
321         rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
322 #endif
323         return rc;
324 }