board/atmel/at91sam9263ek/at91sam9263ek.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  */
   7
   8 #include <common.h>
   9 #include <debug_uart.h>
  10 #include <init.h>
  11 #include <net.h>
  12 #include <vsprintf.h>
  13 #include <linux/sizes.h>
  14 #include <asm/arch/at91sam9263.h>
  15 #include <asm/arch/at91sam9_smc.h>
  16 #include <asm/arch/at91_common.h>
  17 #include <asm/arch/at91_matrix.h>
  18 #include <asm/arch/at91_pio.h>
  19 #include <asm/arch/clk.h>
  20 #include <asm/io.h>
  21 #include <asm/arch/gpio.h>
  22 #include <asm/arch/hardware.h>
  23 #include <lcd.h>
  24 #include <atmel_lcdc.h>
  25 #include <asm/mach-types.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 /* ------------------------------------------------------------------------- */
  30 /*
  31  * Miscelaneous platform dependent initialisations
  32  */
  33
  34 #ifdef CONFIG_CMD_NAND
  35 static void at91sam9263ek_nand_hw_init(void)
  36 {
  37         unsigned long csa;
  38         at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  39         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  40
  41         /* Enable CS3 */
  42         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  43         writel(csa, &matrix->csa[0]);
  44
  45         /* Enable CS3 */
  46
  47         /* Configure SMC CS3 for NAND/SmartMedia */
  48         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  49                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  50                 &smc->cs[3].setup);
  51
  52         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  53                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  54                 &smc->cs[3].pulse);
  55
  56         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  57                 &smc->cs[3].cycle);
  58         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  59                 AT91_SMC_MODE_EXNW_DISABLE |
  60 #ifdef CONFIG_SYS_NAND_DBW_16
  61                        AT91_SMC_MODE_DBW_16 |
  62 #else /* CONFIG_SYS_NAND_DBW_8 */
  63                        AT91_SMC_MODE_DBW_8 |
  64 #endif
  65                        AT91_SMC_MODE_TDF_CYCLE(2),
  66                 &smc->cs[3].mode);
  67
  68         at91_periph_clk_enable(ATMEL_ID_PIOA);
  69         at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  70
  71         /* Configure RDY/BSY */
  72         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  73
  74         /* Enable NandFlash */
  75         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  76 }
  77 #endif
  78
  79 #ifdef CONFIG_LCD
  80 vidinfo_t panel_info = {
  81         .vl_col =               240,
  82         .vl_row =               320,
  83         .vl_clk =               4965000,
  84         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
  85                                 ATMEL_LCDC_INVFRAME_INVERTED,
  86         .vl_bpix =              3,
  87         .vl_tft =               1,
  88         .vl_hsync_len =         5,
  89         .vl_left_margin =       1,
  90         .vl_right_margin =      33,
  91         .vl_vsync_len =         1,
  92         .vl_upper_margin =      1,
  93         .vl_lower_margin =      0,
  94         .mmio =                 ATMEL_BASE_LCDC,
  95 };
  96
  97 void lcd_enable(void)
  98 {
  99         at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
 100 }
 101
 102 void lcd_disable(void)
 103 {
 104         at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 105 }
 106
 107 static void at91sam9263ek_lcd_hw_init(void)
 108 {
 109         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 110         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 111         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 112         at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 113         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 114         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 115         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 116         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 117         at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 118         at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 119         at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 120         at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 121         at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 122         at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 123         at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 124         at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 125         at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 126         at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 127         at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 128         at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 129         at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 130         at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 131
 132         at91_periph_clk_enable(ATMEL_ID_LCDC);
 133         gd->fb_base = ATMEL_BASE_SRAM0;
 134 }
 135
 136 #ifdef CONFIG_LCD_INFO
 137 #include <nand.h>
 138 #include <version.h>
 139
 140 #ifdef CONFIG_MTD_NOR_FLASH
 141 extern flash_info_t flash_info[];
 142 #endif
 143
 144 void lcd_show_board_info(void)
 145 {
 146         ulong dram_size, nand_size;
 147 #ifdef CONFIG_MTD_NOR_FLASH
 148         ulong flash_size;
 149 #endif
 150         int i;
 151         char temp[32];
 152
 153         lcd_printf ("%s\n", U_BOOT_VERSION);
 154         lcd_printf ("(C) 2008 ATMEL Corp\n");
 155         lcd_printf ("at91support@atmel.com\n");
 156         lcd_printf ("%s CPU at %s MHz\n",
 157                 ATMEL_CPU_NAME,
 158                 strmhz(temp, get_cpu_clk_rate()));
 159
 160         dram_size = 0;
 161         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 162                 dram_size += gd->bd->bi_dram[i].size;
 163         nand_size = 0;
 164         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 165                 nand_size += get_nand_dev_by_index(i)->size;
 166 #ifdef CONFIG_MTD_NOR_FLASH
 167         flash_size = 0;
 168         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 169                 flash_size += flash_info[i].size;
 170 #endif
 171         lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 172                 dram_size >> 20,
 173                 nand_size >> 20 );
 174 #ifdef CONFIG_MTD_NOR_FLASH
 175         lcd_printf (",\n  %ld MB NOR",
 176                 flash_size >> 20);
 177 #endif
 178         lcd_puts ("\n");
 179 }
 180 #endif /* CONFIG_LCD_INFO */
 181 #endif
 182
 183 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
 184 void board_debug_uart_init(void)
 185 {
 186         at91_seriald_hw_init();
 187 }
 188 #endif
 189
 190 #ifdef CONFIG_BOARD_EARLY_INIT_F
 191 int board_early_init_f(void)
 192 {
 193 #ifdef CONFIG_DEBUG_UART
 194         debug_uart_init();
 195 #endif
 196         return 0;
 197 }
 198 #endif
 199
 200 int board_init(void)
 201 {
 202         /* arch number of AT91SAM9263EK-Board */
 203         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 204         /* adress of boot parameters */
 205         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 206
 207 #ifdef CONFIG_CMD_NAND
 208         at91sam9263ek_nand_hw_init();
 209 #endif
 210 #ifdef CONFIG_USB_OHCI_NEW
 211         at91_uhp_hw_init();
 212 #endif
 213 #ifdef CONFIG_LCD
 214         at91sam9263ek_lcd_hw_init();
 215 #endif
 216         return 0;
 217 }
 218
 219 int dram_init(void)
 220 {
 221         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 222                 CONFIG_SYS_SDRAM_SIZE);
 223
 224         return 0;
 225 }
 226
 227 #ifdef CONFIG_RESET_PHY_R
 228 void reset_phy(void)
 229 {
 230 }
 231 #endif