board/atmel/at91sam9263ek/at91sam9263ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <linux/sizes.h>
  11 #include <asm/arch/at91sam9263.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_matrix.h>
  15 #include <asm/arch/at91_pio.h>
  16 #include <asm/arch/clk.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/hardware.h>
  20 #include <lcd.h>
  21 #include <atmel_lcdc.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 /* ------------------------------------------------------------------------- */
  26 /*
  27  * Miscelaneous platform dependent initialisations
  28  */
  29
  30 #ifdef CONFIG_CMD_NAND
  31 static void at91sam9263ek_nand_hw_init(void)
  32 {
  33         unsigned long csa;
  34         at91_smc_t    *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  35         at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  36
  37         /* Enable CS3 */
  38         csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  39         writel(csa, &matrix->csa[0]);
  40
  41         /* Enable CS3 */
  42
  43         /* Configure SMC CS3 for NAND/SmartMedia */
  44         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  45                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  46                 &smc->cs[3].setup);
  47
  48         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  49                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  50                 &smc->cs[3].pulse);
  51
  52         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  53                 &smc->cs[3].cycle);
  54         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  55                 AT91_SMC_MODE_EXNW_DISABLE |
  56 #ifdef CONFIG_SYS_NAND_DBW_16
  57                        AT91_SMC_MODE_DBW_16 |
  58 #else /* CONFIG_SYS_NAND_DBW_8 */
  59                        AT91_SMC_MODE_DBW_8 |
  60 #endif
  61                        AT91_SMC_MODE_TDF_CYCLE(2),
  62                 &smc->cs[3].mode);
  63
  64         at91_periph_clk_enable(ATMEL_ID_PIOA);
  65         at91_periph_clk_enable(ATMEL_ID_PIOCDE);
  66
  67         /* Configure RDY/BSY */
  68         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  69
  70         /* Enable NandFlash */
  71         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  72 }
  73 #endif
  74
  75 #ifdef CONFIG_LCD
  76 vidinfo_t panel_info = {
  77         .vl_col =               240,
  78         .vl_row =               320,
  79         .vl_clk =               4965000,
  80         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
  81                                 ATMEL_LCDC_INVFRAME_INVERTED,
  82         .vl_bpix =              3,
  83         .vl_tft =               1,
  84         .vl_hsync_len =         5,
  85         .vl_left_margin =       1,
  86         .vl_right_margin =      33,
  87         .vl_vsync_len =         1,
  88         .vl_upper_margin =      1,
  89         .vl_lower_margin =      0,
  90         .mmio =                 ATMEL_BASE_LCDC,
  91 };
  92
  93 void lcd_enable(void)
  94 {
  95         at91_set_pio_value(AT91_PIO_PORTA, 30, 1);  /* power up */
  96 }
  97
  98 void lcd_disable(void)
  99 {
 100         at91_set_pio_value(AT91_PIO_PORTA, 30, 0);  /* power down */
 101 }
 102
 103 static void at91sam9263ek_lcd_hw_init(void)
 104 {
 105         at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 106         at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 107         at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 108         at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 109         at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 110         at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 111         at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 112         at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 113         at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 114         at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 115         at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 116         at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 117         at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 118         at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 119         at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 120         at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 121         at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 122         at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 123         at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 124         at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 125         at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 126         at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 127
 128         at91_periph_clk_enable(ATMEL_ID_LCDC);
 129         gd->fb_base = ATMEL_BASE_SRAM0;
 130 }
 131
 132 #ifdef CONFIG_LCD_INFO
 133 #include <nand.h>
 134 #include <version.h>
 135
 136 #ifdef CONFIG_MTD_NOR_FLASH
 137 extern flash_info_t flash_info[];
 138 #endif
 139
 140 void lcd_show_board_info(void)
 141 {
 142         ulong dram_size, nand_size;
 143 #ifdef CONFIG_MTD_NOR_FLASH
 144         ulong flash_size;
 145 #endif
 146         int i;
 147         char temp[32];
 148
 149         lcd_printf ("%s\n", U_BOOT_VERSION);
 150         lcd_printf ("(C) 2008 ATMEL Corp\n");
 151         lcd_printf ("at91support@atmel.com\n");
 152         lcd_printf ("%s CPU at %s MHz\n",
 153                 ATMEL_CPU_NAME,
 154                 strmhz(temp, get_cpu_clk_rate()));
 155
 156         dram_size = 0;
 157         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 158                 dram_size += gd->bd->bi_dram[i].size;
 159         nand_size = 0;
 160         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 161                 nand_size += nand_info[i]->size;
 162 #ifdef CONFIG_MTD_NOR_FLASH
 163         flash_size = 0;
 164         for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 165                 flash_size += flash_info[i].size;
 166 #endif
 167         lcd_printf ("  %ld MB SDRAM, %ld MB NAND",
 168                 dram_size >> 20,
 169                 nand_size >> 20 );
 170 #ifdef CONFIG_MTD_NOR_FLASH
 171         lcd_printf (",\n  %ld MB NOR",
 172                 flash_size >> 20);
 173 #endif
 174         lcd_puts ("\n");
 175 }
 176 #endif /* CONFIG_LCD_INFO */
 177 #endif
 178
 179 int board_early_init_f(void)
 180 {
 181         return 0;
 182 }
 183
 184 int board_init(void)
 185 {
 186         /* arch number of AT91SAM9263EK-Board */
 187         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
 188         /* adress of boot parameters */
 189         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 190
 191 #ifdef CONFIG_CMD_NAND
 192         at91sam9263ek_nand_hw_init();
 193 #endif
 194 #ifdef CONFIG_HAS_DATAFLASH
 195         at91_set_pio_output(AT91_PIO_PORTE, 20, 1);     /* select spi0 clock */
 196         at91_spi0_hw_init(1 << 0);
 197 #endif
 198 #ifdef CONFIG_USB_OHCI_NEW
 199         at91_uhp_hw_init();
 200 #endif
 201 #ifdef CONFIG_LCD
 202         at91sam9263ek_lcd_hw_init();
 203 #endif
 204         return 0;
 205 }
 206
 207 int dram_init(void)
 208 {
 209         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 210                 CONFIG_SYS_SDRAM_SIZE);
 211
 212         return 0;
 213 }
 214
 215 #ifdef CONFIG_RESET_PHY_R
 216 void reset_phy(void)
 217 {
 218 }
 219 #endif