2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/at91sam9261.h>
27 #include <asm/arch/at91sam9261_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_common.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/clk.h>
33 #include <asm/arch/gpio.h>
34 #include <asm/arch/io.h>
36 #include <atmel_lcdc.h>
37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
41 DECLARE_GLOBAL_DATA_PTR;
43 /* ------------------------------------------------------------------------- */
45 * Miscelaneous platform dependent initialisations
48 #ifdef CONFIG_CMD_NAND
49 static void at91sam9261ek_nand_hw_init(void)
54 csa = at91_sys_read(AT91_MATRIX_EBICSA);
55 at91_sys_write(AT91_MATRIX_EBICSA,
56 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
58 /* Configure SMC CS3 for NAND/SmartMedia */
59 at91_sys_write(AT91_SMC_SETUP(3),
60 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
61 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
62 at91_sys_write(AT91_SMC_PULSE(3),
63 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
64 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
65 at91_sys_write(AT91_SMC_CYCLE(3),
66 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
67 at91_sys_write(AT91_SMC_MODE(3),
68 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
69 AT91_SMC_EXNWMODE_DISABLE |
70 #ifdef CONFIG_SYS_NAND_DBW_16
72 #else /* CONFIG_SYS_NAND_DBW_8 */
77 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
79 /* Configure RDY/BSY */
80 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
82 /* Enable NandFlash */
83 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
85 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
86 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
90 #ifdef CONFIG_DRIVER_DM9000
91 static void at91sam9261ek_dm9000_hw_init(void)
93 /* Configure SMC CS2 for DM9000 */
94 at91_sys_write(AT91_SMC_SETUP(2),
95 AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
96 AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
97 at91_sys_write(AT91_SMC_PULSE(2),
98 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
99 AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
100 at91_sys_write(AT91_SMC_CYCLE(2),
101 AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
102 at91_sys_write(AT91_SMC_MODE(2),
103 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
104 AT91_SMC_EXNWMODE_DISABLE |
105 AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
108 /* Configure Reset signal as output */
109 at91_set_gpio_output(AT91_PIN_PC10, 0);
111 /* Configure Interrupt pin as input, no pull-up */
112 at91_set_gpio_input(AT91_PIN_PC11, 0);
117 vidinfo_t panel_info = {
121 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
122 ATMEL_LCDC_INVFRAME_INVERTED,
131 mmio: AT91SAM9261_LCDC_BASE,
134 void lcd_enable(void)
136 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
139 void lcd_disable(void)
141 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
144 static void at91sam9261ek_lcd_hw_init(void)
146 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
147 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
148 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
149 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
150 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
151 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
152 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
153 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
154 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
155 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
156 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
157 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
158 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
159 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
160 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
161 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
162 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
163 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
164 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
165 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
166 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
167 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
169 at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
171 gd->fb_base = AT91SAM9261_SRAM_BASE;
174 #ifdef CONFIG_LCD_INFO
178 void lcd_show_board_info(void)
180 ulong dram_size, nand_size;
184 lcd_printf ("%s\n", U_BOOT_VERSION);
185 lcd_printf ("(C) 2008 ATMEL Corp\n");
186 lcd_printf ("at91support@atmel.com\n");
187 lcd_printf ("%s CPU at %s MHz\n",
189 strmhz(temp, get_cpu_clk_rate()));
192 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
193 dram_size += gd->bd->bi_dram[i].size;
195 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
196 nand_size += nand_info[i].size;
197 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
201 #endif /* CONFIG_LCD_INFO */
209 /* arch number of AT91SAM9261EK-Board */
210 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
211 /* adress of boot parameters */
212 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
214 at91_serial_hw_init();
215 #ifdef CONFIG_CMD_NAND
216 at91sam9261ek_nand_hw_init();
218 #ifdef CONFIG_HAS_DATAFLASH
219 at91_spi0_hw_init(1 << 0);
221 #ifdef CONFIG_DRIVER_DM9000
222 at91sam9261ek_dm9000_hw_init();
225 at91sam9261ek_lcd_hw_init();
232 gd->bd->bi_dram[0].start = PHYS_SDRAM;
233 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
237 #ifdef CONFIG_RESET_PHY_R
240 #ifdef CONFIG_DRIVER_DM9000
242 * Initialize ethernet HW addr prior to starting Linux,