2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/at91sam9261.h>
28 #include <asm/arch/at91sam9261_matrix.h>
29 #include <asm/arch/at91sam9_smc.h>
30 #include <asm/arch/at91_common.h>
31 #include <asm/arch/at91_pmc.h>
32 #include <asm/arch/at91_rstc.h>
33 #include <asm/arch/clk.h>
34 #include <asm/arch/gpio.h>
36 #include <atmel_lcdc.h>
37 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
42 DECLARE_GLOBAL_DATA_PTR;
44 /* ------------------------------------------------------------------------- */
46 * Miscelaneous platform dependent initialisations
49 #ifdef CONFIG_CMD_NAND
50 static void at91sam9261ek_nand_hw_init(void)
52 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
53 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
54 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
58 csa = readl(&matrix->ebicsa);
59 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
61 writel(csa, &matrix->ebicsa);
63 /* Configure SMC CS3 for NAND/SmartMedia */
64 #ifdef CONFIG_AT91SAM9G10EK
65 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
66 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
68 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
69 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
71 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
74 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
75 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
77 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
78 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
80 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
83 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
84 AT91_SMC_MODE_EXNW_DISABLE |
85 #ifdef CONFIG_SYS_NAND_DBW_16
86 AT91_SMC_MODE_DBW_16 |
87 #else /* CONFIG_SYS_NAND_DBW_8 */
90 AT91_SMC_MODE_TDF_CYCLE(2),
93 writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
95 /* Configure RDY/BSY */
96 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
98 /* Enable NandFlash */
99 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
101 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
102 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
106 #ifdef CONFIG_DRIVER_DM9000
107 static void at91sam9261ek_dm9000_hw_init(void)
109 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
111 /* Configure SMC CS2 for DM9000 */
112 #ifdef CONFIG_AT91SAM9G10EK
113 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
114 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
116 writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
117 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
119 writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
121 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
122 AT91_SMC_MODE_EXNW_DISABLE |
123 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
124 AT91_SMC_MODE_TDF_CYCLE(1),
127 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
128 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
130 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
131 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
133 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
135 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
136 AT91_SMC_MODE_EXNW_DISABLE |
137 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
138 AT91_SMC_MODE_TDF_CYCLE(1),
142 /* Configure Reset signal as output */
143 at91_set_gpio_output(AT91_PIN_PC10, 0);
145 /* Configure Interrupt pin as input, no pull-up */
146 at91_set_gpio_input(AT91_PIN_PC11, 0);
151 vidinfo_t panel_info = {
155 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
156 ATMEL_LCDC_INVFRAME_INVERTED,
165 mmio: ATMEL_BASE_LCDC,
168 void lcd_enable(void)
170 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
173 void lcd_disable(void)
175 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
178 static void at91sam9261ek_lcd_hw_init(void)
180 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
182 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
183 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
184 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
185 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
186 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
187 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
188 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
189 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
190 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
191 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
192 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
193 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
194 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
195 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
196 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
197 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
198 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
199 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
200 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
201 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
202 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
203 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
205 writel(AT91_PMC_HCK1, &pmc->scer);
207 /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
208 #ifdef CONFIG_AT91SAM9261EK
209 gd->fb_base = ATMEL_BASE_SRAM;
213 #ifdef CONFIG_LCD_INFO
217 void lcd_show_board_info(void)
219 ulong dram_size, nand_size;
223 lcd_printf ("%s\n", U_BOOT_VERSION);
224 lcd_printf ("(C) 2008 ATMEL Corp\n");
225 lcd_printf ("at91support@atmel.com\n");
226 lcd_printf ("%s CPU at %s MHz\n",
228 strmhz(temp, get_cpu_clk_rate()));
231 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
232 dram_size += gd->bd->bi_dram[i].size;
234 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
235 nand_size += nand_info[i].size;
236 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
240 #endif /* CONFIG_LCD_INFO */
248 #ifdef CONFIG_AT91SAM9G10EK
249 /* arch number of AT91SAM9G10EK-Board */
250 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
252 /* arch number of AT91SAM9261EK-Board */
253 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
255 /* adress of boot parameters */
256 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
258 at91_seriald_hw_init();
259 #ifdef CONFIG_CMD_NAND
260 at91sam9261ek_nand_hw_init();
262 #ifdef CONFIG_HAS_DATAFLASH
263 at91_spi0_hw_init(1 << 0);
265 #ifdef CONFIG_DRIVER_DM9000
266 at91sam9261ek_dm9000_hw_init();
269 at91sam9261ek_lcd_hw_init();
274 #ifdef CONFIG_DRIVER_DM9000
275 int board_eth_init(bd_t *bis)
277 return dm9000_initialize(bis);
283 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
284 CONFIG_SYS_SDRAM_SIZE);
289 #ifdef CONFIG_RESET_PHY_R
292 #ifdef CONFIG_DRIVER_DM9000
294 * Initialize ethernet HW addr prior to starting Linux,