board/atmel/at91sam9260ek/at91sam9260ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91sam9260_matrix.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/clk.h>
  15 #include <asm/arch/gpio.h>
  16
  17 DECLARE_GLOBAL_DATA_PTR;
  18
  19 /* ------------------------------------------------------------------------- */
  20 /*
  21  * Miscelaneous platform dependent initialisations
  22  */
  23
  24 #ifdef CONFIG_CMD_NAND
  25 static void at91sam9260ek_nand_hw_init(void)
  26 {
  27         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  28         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  29         unsigned long csa;
  30
  31         /* Assign CS3 to NAND/SmartMedia Interface */
  32         csa = readl(&matrix->ebicsa);
  33         csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  34         writel(csa, &matrix->ebicsa);
  35
  36         /* Configure SMC CS3 for NAND/SmartMedia */
  37         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  38                 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  39                 &smc->cs[3].setup);
  40         writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  41                 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  42                 &smc->cs[3].pulse);
  43         writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  44                 &smc->cs[3].cycle);
  45         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  46                 AT91_SMC_MODE_EXNW_DISABLE |
  47 #ifdef CONFIG_SYS_NAND_DBW_16
  48                 AT91_SMC_MODE_DBW_16 |
  49 #else /* CONFIG_SYS_NAND_DBW_8 */
  50                 AT91_SMC_MODE_DBW_8 |
  51 #endif
  52                 AT91_SMC_MODE_TDF_CYCLE(2),
  53                 &smc->cs[3].mode);
  54
  55         /* Configure RDY/BSY */
  56         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  57
  58         /* Enable NandFlash */
  59         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  60
  61 }
  62 #endif
  63
  64 int board_early_init_f(void)
  65 {
  66         return 0;
  67 }
  68
  69 int board_init(void)
  70 {
  71         /* adress of boot parameters */
  72         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  73
  74 #ifdef CONFIG_CMD_NAND
  75         at91sam9260ek_nand_hw_init();
  76 #endif
  77 #ifdef CONFIG_HAS_DATAFLASH
  78         at91_spi0_hw_init((1 << 0) | (1 << 1));
  79 #endif
  80
  81         return 0;
  82 }
  83
  84 int dram_init(void)
  85 {
  86         gd->ram_size = get_ram_size(
  87                 (void *)CONFIG_SYS_SDRAM_BASE,
  88                 CONFIG_SYS_SDRAM_SIZE);
  89         return 0;
  90 }
  91
  92 #ifdef CONFIG_RESET_PHY_R
  93 void reset_phy(void)
  94 {
  95 }
  96 #endif