2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/at91sam9260_matrix.h>
28 #include <asm/arch/at91sam9_smc.h>
29 #include <asm/arch/at91_common.h>
30 #include <asm/arch/at91_pmc.h>
31 #include <asm/arch/at91_rstc.h>
32 #include <asm/arch/gpio.h>
33 #include <atmel_mci.h>
35 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
40 DECLARE_GLOBAL_DATA_PTR;
42 /* ------------------------------------------------------------------------- */
44 * Miscelaneous platform dependent initialisations
47 #ifdef CONFIG_CMD_NAND
48 static void at91sam9260ek_nand_hw_init(void)
50 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
51 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
54 /* Assign CS3 to NAND/SmartMedia Interface */
55 csa = readl(&matrix->ebicsa);
56 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
57 writel(csa, &matrix->ebicsa);
59 /* Configure SMC CS3 for NAND/SmartMedia */
60 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
61 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
63 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
64 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
66 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
68 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
69 AT91_SMC_MODE_EXNW_DISABLE |
70 #ifdef CONFIG_SYS_NAND_DBW_16
71 AT91_SMC_MODE_DBW_16 |
72 #else /* CONFIG_SYS_NAND_DBW_8 */
75 AT91_SMC_MODE_TDF_CYCLE(2),
78 /* Configure RDY/BSY */
79 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
81 /* Enable NandFlash */
82 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
88 static void at91sam9260ek_macb_hw_init(void)
90 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
91 struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
92 struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
95 /* Enable EMAC clock */
96 writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
100 * RXDV (PA17) => PHY normal mode (not Test mode)
101 * ERX0 (PA14) => PHY ADDR0
102 * ERX1 (PA15) => PHY ADDR1
103 * ERX2 (PA25) => PHY ADDR2
104 * ERX3 (PA26) => PHY ADDR3
105 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
107 * PHY has internal pull-down
109 writel(pin_to_mask(AT91_PIN_PA14) |
110 pin_to_mask(AT91_PIN_PA15) |
111 pin_to_mask(AT91_PIN_PA17) |
112 pin_to_mask(AT91_PIN_PA25) |
113 pin_to_mask(AT91_PIN_PA26) |
114 pin_to_mask(AT91_PIN_PA28),
117 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
119 /* Need to reset PHY -> 500ms reset */
120 writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
121 AT91_RSTC_MR_URSTEN, &rstc->mr);
123 writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
125 /* Wait for end hardware reset */
126 while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
129 /* Restore NRST value */
130 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
133 /* Re-enable pull-up */
134 writel(pin_to_mask(AT91_PIN_PA14) |
135 pin_to_mask(AT91_PIN_PA15) |
136 pin_to_mask(AT91_PIN_PA17) |
137 pin_to_mask(AT91_PIN_PA25) |
138 pin_to_mask(AT91_PIN_PA26) |
139 pin_to_mask(AT91_PIN_PA28),
142 /* Initialize EMAC=MACB hardware */
147 #ifdef CONFIG_GENERIC_ATMEL_MCI
148 int board_mmc_init(bd_t *bd)
152 return atmel_mci_init((void *)ATMEL_BASE_MCI);
156 int board_early_init_f(void)
158 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
160 /* Enable clocks for all PIOs */
161 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
162 (1 << ATMEL_ID_PIOC),
170 #ifdef CONFIG_AT91SAM9G20EK_2MMC
171 /* arch number of AT91SAM9G20EK_2MMC-Board */
172 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK_2MMC;
174 #ifdef CONFIG_AT91SAM9G20EK
175 /* arch number of AT91SAM9G20EK-Board */
176 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G20EK;
178 /* arch number of AT91SAM9260EK-Board */
179 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9260EK;
182 /* adress of boot parameters */
183 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
185 at91_seriald_hw_init();
186 #ifdef CONFIG_CMD_NAND
187 at91sam9260ek_nand_hw_init();
189 #ifdef CONFIG_HAS_DATAFLASH
190 at91_spi0_hw_init((1 << 0) | (1 << 1));
193 at91sam9260ek_macb_hw_init();
201 gd->ram_size = get_ram_size(
202 (void *)CONFIG_SYS_SDRAM_BASE,
203 CONFIG_SYS_SDRAM_SIZE);
207 #ifdef CONFIG_RESET_PHY_R
213 int board_eth_init(bd_t *bis)
217 rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);