board/atmark-techno/armadillo-800eva/armadillo-800eva.c

   1 /*
   2  * Copyright (C) 2012  Renesas Solutions Corp.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <cpu_func.h>
  25 #include <init.h>
  26 #include <malloc.h>
  27 #include <asm/processor.h>
  28 #include <asm/mach-types.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <asm/gpio.h>
  32 #include <asm/arch/rmobile.h>
  33
  34 #define s_init_wait(cnt) \
  35                 ({      \
  36                         volatile u32 i = 0x10000 * cnt; \
  37                         while (i > 0)   \
  38                                 i--;    \
  39                 })
  40
  41 #define USBCR1 0xE605810A
  42
  43 void s_init(void)
  44 {
  45         struct r8a7740_rwdt *rwdt0 = (struct r8a7740_rwdt *)RWDT0_BASE;
  46         struct r8a7740_rwdt *rwdt1 = (struct r8a7740_rwdt *)RWDT1_BASE;
  47         struct r8a7740_cpg *cpg = (struct r8a7740_cpg *)CPG_BASE;
  48         struct r8a7740_bsc *bsc = (struct r8a7740_bsc *)BSC_BASE;
  49         struct r8a7740_ddrp *ddrp = (struct r8a7740_ddrp *)DDRP_BASE;
  50         struct r8a7740_dbsc *dbsc = (struct r8a7740_dbsc *)DBSC_BASE;
  51
  52         /* Watchdog init */
  53         writew(0xA500, &rwdt0->rwtcsra0);
  54         writew(0xA500, &rwdt1->rwtcsra0);
  55
  56         /* CPG */
  57         writel(0xFF800080, &cpg->rmstpcr4);
  58         writel(0xFF800080, &cpg->smstpcr4);
  59
  60         /* USB clock */
  61         writel(0x00000080, &cpg->usbckcr);
  62         s_init_wait(1);
  63
  64         /* USBCR1 */
  65         writew(0x0710, USBCR1);
  66
  67         /* FRQCR */
  68         writel(0x00000000, &cpg->frqcrb);
  69         writel(0x62030533, &cpg->frqcra);
  70         writel(0x208A354E, &cpg->frqcrc);
  71         writel(0x80331050, &cpg->frqcrb);
  72         s_init_wait(1);
  73
  74         writel(0x00000000, &cpg->frqcrd);
  75         s_init_wait(1);
  76
  77         /* SUBClk */
  78         writel(0x0000010B, &cpg->subckcr);
  79
  80         /* PLL */
  81         writel(0x00004004, &cpg->pllc01cr);
  82         s_init_wait(1);
  83
  84         writel(0xa0000000, &cpg->pllc2cr);
  85         s_init_wait(2);
  86
  87         /* BSC */
  88         writel(0x0000001B, &bsc->cmncr);
  89
  90         writel(0x20000000, &dbsc->dbcmd);
  91         writel(0x10009C40, &dbsc->dbcmd);
  92         s_init_wait(1);
  93
  94         writel(0x00000007, &dbsc->dbkind);
  95         writel(0x0E030A02, &dbsc->dbconf0);
  96         writel(0x00000001, &dbsc->dbphytype);
  97         writel(0x00000000, &dbsc->dbbl);
  98         writel(0x00000006, &dbsc->dbtr0);
  99         writel(0x00000005, &dbsc->dbtr1);
 100         writel(0x00000000, &dbsc->dbtr2);
 101         writel(0x00000006, &dbsc->dbtr3);
 102         writel(0x00080006, &dbsc->dbtr4);
 103         writel(0x00000015, &dbsc->dbtr5);
 104         writel(0x0000000f, &dbsc->dbtr6);
 105         writel(0x00000004, &dbsc->dbtr7);
 106         writel(0x00000018, &dbsc->dbtr8);
 107         writel(0x00000006, &dbsc->dbtr9);
 108         writel(0x00000006, &dbsc->dbtr10);
 109         writel(0x0000000F, &dbsc->dbtr11);
 110         writel(0x0000000D, &dbsc->dbtr12);
 111         writel(0x000000A0, &dbsc->dbtr13);
 112         writel(0x000A0003, &dbsc->dbtr14);
 113         writel(0x00000003, &dbsc->dbtr15);
 114         writel(0x40005005, &dbsc->dbtr16);
 115         writel(0x0C0C0000, &dbsc->dbtr17);
 116         writel(0x00000200, &dbsc->dbtr18);
 117         writel(0x00000040, &dbsc->dbtr19);
 118         writel(0x00000001, &dbsc->dbrnk0);
 119         writel(0x00000110, &dbsc->dbdficnt);
 120         writel(0x00000101, &ddrp->funcctrl);
 121         writel(0x00000001, &ddrp->dllctrl);
 122         writel(0x00000186, &ddrp->zqcalctrl);
 123         writel(0xB3440051, &ddrp->zqodtctrl);
 124         writel(0x94449443, &ddrp->rdctrl);
 125         writel(0x000000C0, &ddrp->rdtmg);
 126         writel(0x00000101, &ddrp->fifoinit);
 127         writel(0x02060506, &ddrp->outctrl);
 128         writel(0x00004646, &ddrp->dqcalofs1);
 129         writel(0x00004646, &ddrp->dqcalofs2);
 130         writel(0x800000aa, &ddrp->dqcalexp);
 131         writel(0x00000000, &ddrp->dllctrl);
 132         writel(0x00000000, DDRPNCNT);
 133
 134         writel(0x0000000C, &dbsc->dbcmd);
 135         readl(&dbsc->dbwait);
 136         s_init_wait(1);
 137
 138         writel(0x00000002, DDRPNCNT);
 139
 140         writel(0x0000000C, &dbsc->dbcmd);
 141         readl(&dbsc->dbwait);
 142         s_init_wait(1);
 143
 144         writel(0x00000187, &ddrp->zqcalctrl);
 145
 146         writel(0x00009C40, &dbsc->dbcmd);
 147         readl(&dbsc->dbwait);
 148         s_init_wait(1);
 149
 150         writel(0x00009C40, &dbsc->dbcmd);
 151         readl(&dbsc->dbwait);
 152         s_init_wait(1);
 153
 154         writel(0x00000010, &dbsc->dbdficnt);
 155         writel(0x02060507, &ddrp->outctrl);
 156
 157         writel(0x00009C40, &dbsc->dbcmd);
 158         readl(&dbsc->dbwait);
 159         s_init_wait(1);
 160
 161         writel(0x21009C40, &dbsc->dbcmd);
 162         readl(&dbsc->dbwait);
 163         s_init_wait(1);
 164
 165         writel(0x00009C40, &dbsc->dbcmd);
 166         readl(&dbsc->dbwait);
 167         s_init_wait(1);
 168
 169         writel(0x00009C40, &dbsc->dbcmd);
 170         readl(&dbsc->dbwait);
 171         s_init_wait(1);
 172
 173         writel(0x00009C40, &dbsc->dbcmd);
 174         readl(&dbsc->dbwait);
 175         s_init_wait(1);
 176
 177         writel(0x00009C40, &dbsc->dbcmd);
 178         readl(&dbsc->dbwait);
 179         s_init_wait(1);
 180
 181         writel(0x11000044, &dbsc->dbcmd);
 182         readl(&dbsc->dbwait);
 183         s_init_wait(1);
 184
 185         writel(0x2A000000, &dbsc->dbcmd);
 186         readl(&dbsc->dbwait);
 187         s_init_wait(1);
 188
 189         writel(0x2B000000, &dbsc->dbcmd);
 190         readl(&dbsc->dbwait);
 191
 192         writel(0x29000004, &dbsc->dbcmd);
 193         readl(&dbsc->dbwait);
 194
 195         writel(0x28001520, &dbsc->dbcmd);
 196         readl(&dbsc->dbwait);
 197         s_init_wait(1);
 198
 199         writel(0x03000200, &dbsc->dbcmd);
 200         readl(&dbsc->dbwait);
 201         s_init_wait(1);
 202
 203         writel(0x000001FF, &dbsc->dbrfcnf0);
 204         writel(0x00010C30, &dbsc->dbrfcnf1);
 205         writel(0x00000000, &dbsc->dbrfcnf2);
 206
 207         writel(0x00000001, &dbsc->dbrfen);
 208         writel(0x00000001, &dbsc->dbacen);
 209
 210         /* BSC */
 211         writel(0x00410400, &bsc->cs0bcr);
 212         writel(0x00410400, &bsc->cs2bcr);
 213         writel(0x00410400, &bsc->cs5bbcr);
 214         writel(0x02CB0400, &bsc->cs6abcr);
 215
 216         writel(0x00000440, &bsc->cs0wcr);
 217         writel(0x00000440, &bsc->cs2wcr);
 218         writel(0x00000240, &bsc->cs5bwcr);
 219         writel(0x00000240, &bsc->cs6awcr);
 220
 221         writel(0x00000005, &bsc->rbwtcnt);
 222         writel(0x00000002, &bsc->cs0wcr2);
 223         writel(0x00000002, &bsc->cs2wcr2);
 224         writel(0x00000002, &bsc->cs4wcr2);
 225 }
 226
 227 #define GPIO_ICCR (0xE60581A0)
 228 #define ICCR_15BIT (1 << 15) /* any time 1 */
 229 #define IIC0_CONTA (1 << 7)
 230 #define IIC0_CONTB (1 << 6)
 231 #define IIC1_CONTA (1 << 5)
 232 #define IIC1_CONTB (1 << 4)
 233 #define IIC0_PS33E (1 << 1)
 234 #define IIC1_PS33E (1 << 0)
 235 #define GPIO_ICCR_DATA  \
 236                 (ICCR_15BIT |   \
 237                 IIC0_CONTA | IIC0_CONTB | IIC1_CONTA |  \
 238                 IIC1_CONTB | IIC0_PS33E | IIC1_PS33E)
 239
 240 #define MSTPCR1         0xE6150134
 241 #define TMU0_MSTP125    (1 << 25)
 242 #define I2C0_MSTP116    (1 << 16)
 243
 244 #define MSTPCR3         0xE615013C
 245 #define I2C1_MSTP323    (1 << 23)
 246 #define GETHER_MSTP309  (1 << 9)
 247
 248 #define GPIO_SCIFA1_TXD (0xE60520C4)
 249 #define GPIO_SCIFA1_RXD (0xE60520C3)
 250
 251 int board_early_init_f(void)
 252 {
 253         /* TMU */
 254         clrbits_le32(MSTPCR1, TMU0_MSTP125);
 255
 256         /* GETHER */
 257         clrbits_le32(MSTPCR3, GETHER_MSTP309);
 258
 259         /* I2C 0/1 */
 260         clrbits_le32(MSTPCR1, I2C0_MSTP116);
 261         clrbits_le32(MSTPCR3, I2C1_MSTP323);
 262
 263         /* SCIFA1 */
 264         writeb(1, GPIO_SCIFA1_TXD); /* SCIFA1_TXD */
 265         writeb(1, GPIO_SCIFA1_RXD); /* SCIFA1_RXD */
 266
 267         /* IICCR */
 268         writew(GPIO_ICCR_DATA, GPIO_ICCR);
 269
 270         return 0;
 271 }
 272
 273 DECLARE_GLOBAL_DATA_PTR;
 274 int board_init(void)
 275 {
 276         /* board id for linux */
 277         gd->bd->bi_arch_number = MACH_TYPE_ARMADILLO800EVA;
 278         /* adress of boot parameters */
 279         gd->bd->bi_boot_params = ARMADILLO_800EVA_SDRAM_BASE + 0x100;
 280
 281         /* Init PFC controller */
 282         r8a7740_pinmux_init();
 283
 284         /* GETHER Enable */
 285         gpio_request(GPIO_FN_ET_CRS, NULL);
 286         gpio_request(GPIO_FN_ET_MDC, NULL);
 287         gpio_request(GPIO_FN_ET_MDIO, NULL);
 288         gpio_request(GPIO_FN_ET_TX_ER, NULL);
 289         gpio_request(GPIO_FN_ET_RX_ER, NULL);
 290         gpio_request(GPIO_FN_ET_ERXD0, NULL);
 291         gpio_request(GPIO_FN_ET_ERXD1, NULL);
 292         gpio_request(GPIO_FN_ET_ERXD2, NULL);
 293         gpio_request(GPIO_FN_ET_ERXD3, NULL);
 294         gpio_request(GPIO_FN_ET_TX_CLK, NULL);
 295         gpio_request(GPIO_FN_ET_TX_EN, NULL);
 296         gpio_request(GPIO_FN_ET_ETXD0, NULL);
 297         gpio_request(GPIO_FN_ET_ETXD1, NULL);
 298         gpio_request(GPIO_FN_ET_ETXD2, NULL);
 299         gpio_request(GPIO_FN_ET_ETXD3, NULL);
 300         gpio_request(GPIO_FN_ET_PHY_INT, NULL);
 301         gpio_request(GPIO_FN_ET_COL, NULL);
 302         gpio_request(GPIO_FN_ET_RX_DV, NULL);
 303         gpio_request(GPIO_FN_ET_RX_CLK, NULL);
 304
 305         gpio_request(GPIO_PORT18, NULL); /* PHY_RST */
 306         gpio_direction_output(GPIO_PORT18, 1);
 307
 308         return 0;
 309 }
 310
 311 int dram_init(void)
 312 {
 313         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 314         gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
 315
 316         return 0;
 317 }
 318
 319 int board_late_init(void)
 320 {
 321         return 0;
 322 }
 323
 324 void reset_cpu(ulong addr)
 325 {
 326 }