3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
15 * Philippe Robin, <philippe.robin@arm.com>
17 * SPDX-License-Identifier: GPL-2.0+
24 #include <dm/platform_data/serial_pl01x.h>
26 #include "integrator-sc.h"
27 #include <asm/mach-types.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 static const struct pl01x_serial_platdata serial_platdata = {
33 #ifdef CONFIG_ARCH_CINTEGRATOR
38 .clock = 0, /* Not used for PL010 */
42 U_BOOT_DEVICE(integrator_serials) = {
43 .name = "serial_pl01x",
44 .platdata = &serial_platdata,
47 void peripheral_power_enable (void);
49 #if defined(CONFIG_SHOW_BOOT_PROGRESS)
50 void show_boot_progress(int progress)
52 printf("Boot reached stage %d\n", progress);
56 #define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
59 * Miscellaneous platform dependent initialisations
66 /* arch number of Integrator Board */
67 #ifdef CONFIG_ARCH_CINTEGRATOR
68 gd->bd->bi_arch_number = MACH_TYPE_CINTEGRATOR;
70 gd->bd->bi_arch_number = MACH_TYPE_INTEGRATOR;
73 /* adress of boot parameters */
74 gd->bd->bi_boot_params = 0x00000100;
76 #ifdef CONFIG_CM_REMAP
77 extern void cm_remap(void);
78 cm_remap(); /* remaps writeable memory to 0x00000000 */
81 #ifdef CONFIG_ARCH_CINTEGRATOR
83 * Flash protection on the Integrator/CP is in a simple register
85 val = readl(CP_FLASHPROG);
86 val |= (CP_FLASHPROG_FLVPPEN | CP_FLASHPROG_FLWREN);
87 writel(val, CP_FLASHPROG);
90 * The Integrator/AP has some special protection mechanisms
91 * for the external memories, first the External Bus Interface (EBI)
92 * then the system controller (SC).
94 * The system comes up with the flash memory non-writable and
95 * configuration locked. If we want U-Boot to be used for flash
96 * access we cannot have the flash memory locked.
98 writel(EBI_UNLOCK_MAGIC, EBI_BASE + EBI_LOCK_REG);
99 val = readl(EBI_BASE + EBI_CSR1_REG);
100 val &= EBI_CSR_WREN_MASK;
101 val |= EBI_CSR_WREN_ENABLE;
102 writel(val, EBI_BASE + EBI_CSR1_REG);
103 writel(0, EBI_BASE + EBI_LOCK_REG);
106 * Set up the system controller to remove write protection from
107 * the flash memory and enable Vpp
109 writel(SC_CTRL_FLASHVPP | SC_CTRL_FLASHWP, SC_CTRLS);
117 int misc_init_r (void)
119 setenv("verify", "n");
124 * The Integrator remaps the Flash memory to 0x00000000 and executes U-Boot
125 * from there, which means we cannot test the RAM underneath the ROM at this
126 * point. It will be unmapped later on, when we are executing from the
127 * relocated in RAM U-Boot. We simply assume that this RAM is usable if the
128 * RAM on higher addresses works fine.
130 #define REMAPPED_FLASH_SZ 0x40000
134 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
135 #ifdef CONFIG_CM_SPD_DETECT
137 extern void dram_query(void);
141 dram_query(); /* Assembler accesses to CM registers */
142 /* Queries the SPD values */
144 /* Obtain the SDRAM size from the CM SDRAM register */
146 cm_reg_sdram = readl(CM_BASE + OS_SDRAM);
147 /* Register SDRAM size
149 * 0xXXXXXXbbb000bb 16 MB
150 * 0xXXXXXXbbb001bb 32 MB
151 * 0xXXXXXXbbb010bb 64 MB
152 * 0xXXXXXXbbb011bb 128 MB
153 * 0xXXXXXXbbb100bb 256 MB
156 sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
157 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
159 0x01000000 << sdram_shift);
162 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE +
165 #endif /* CM_SPD_DETECT */
166 /* We only have one bank of RAM, set it to whatever was detected */
167 gd->bd->bi_dram[0].size = gd->ram_size;
172 #ifdef CONFIG_CMD_NET
173 int board_eth_init(bd_t *bis)
176 #ifdef CONFIG_SMC91111
177 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
179 rc += pci_eth_init(bis);