1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Linus Walleij <linus.walleij@linaro.org>
6 * Register definitions for the External Bus Interface (EBI)
7 * found in the ARM Integrator AP and CP reference designs
13 #define EBI_BASE 0x12000000
15 #define EBI_CSR0_REG 0x00 /* CS0 = Boot ROM */
16 #define EBI_CSR1_REG 0x04 /* CS1 = Flash */
17 #define EBI_CSR2_REG 0x08 /* CS2 = SSRAM */
18 #define EBI_CSR3_REG 0x0C /* CS3 = Expansion memory */
20 * The four upper bits are the waitstates for each chip select
21 * 0x00 = 2 cycles, 0x10 = 3 cycles, ... 0xe0 = 16 cycles, 0xf0 = 16 cycles
23 #define EBI_CSR_WAIT_MASK 0xF0
24 /* Whether memory is synchronous or asynchronous */
25 #define EBI_CSR_SYNC_MASK 0xF7
26 #define EBI_CSR_ASYNC 0x00
27 #define EBI_CSR_SYNC 0x08
28 /* Whether memory is write enabled or not */
29 #define EBI_CSR_WREN_MASK 0xFB
30 #define EBI_CSR_WREN_DISABLE 0x00
31 #define EBI_CSR_WREN_ENABLE 0x04
32 /* Memory bit width for each chip select */
33 #define EBI_CSR_MEMSIZE_MASK 0xFC
34 #define EBI_CSR_MEMSIZE_8BIT 0x00
35 #define EBI_CSR_MEMSIZE_16BIT 0x01
36 #define EBI_CSR_MEMSIZE_32BIT 0x02
39 * The lock register need to be written with 0xa05f before anything in the
42 #define EBI_LOCK_REG 0x20
43 #define EBI_UNLOCK_MAGIC 0xA05F