board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <bmp_logo.h>
  25 #include <dm/root.h>
  26 #include <env.h>
  27 #include <i2c_eeprom.h>
  28 #include <i2c.h>
  29 #include <micrel.h>
  30 #include <miiphy.h>
  31 #include <lcd.h>
  32 #include <led.h>
  33 #include <power/pmic.h>
  34 #include <power/regulator.h>
  35 #include <power/da9063_pmic.h>
  36 #include <splash.h>
  37 #include <video_fb.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 enum {
  42         BOARD_TYPE_4 = 4,
  43         BOARD_TYPE_7 = 7,
  44 };
  45
  46 #define ARI_BT_4 "aristainetos2_4@2"
  47 #define ARI_BT_7 "aristainetos2_7@1"
  48
  49 int board_phy_config(struct phy_device *phydev)
  50 {
  51         /* control data pad skew - devaddr = 0x02, register = 0x04 */
  52         ksz9031_phy_extended_write(phydev, 0x02,
  53                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  54                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  55         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  56         ksz9031_phy_extended_write(phydev, 0x02,
  57                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  58                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  59         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  60         ksz9031_phy_extended_write(phydev, 0x02,
  61                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  62                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  63         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  64         ksz9031_phy_extended_write(phydev, 0x02,
  65                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  66                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  67
  68         if (phydev->drv->config)
  69                 phydev->drv->config(phydev);
  70
  71         return 0;
  72 }
  73
  74 static int rotate_logo_one(unsigned char *out, unsigned char *in)
  75 {
  76         int   i, j;
  77
  78         for (i = 0; i < BMP_LOGO_WIDTH; i++)
  79                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  80                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  81                         in[i * BMP_LOGO_WIDTH + j];
  82         return 0;
  83 }
  84
  85 /*
  86  * Rotate the BMP_LOGO (only)
  87  * Will only work, if the logo is square, as
  88  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  89  */
  90 void rotate_logo(int rotations)
  91 {
  92         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  93         struct bmp_header *header;
  94         unsigned char *in_logo;
  95         int   i, j;
  96
  97         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
  98                 return;
  99
 100         header = (struct bmp_header *)bmp_logo_bitmap;
 101         in_logo = bmp_logo_bitmap + header->data_offset;
 102
 103         /* one 90 degree rotation */
 104         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 105                 rotate_logo_one(out_logo, in_logo);
 106
 107         /* second 90 degree rotation */
 108         if (rotations == 2  ||  rotations == 3)
 109                 rotate_logo_one(in_logo, out_logo);
 110
 111         /* third 90 degree rotation */
 112         if (rotations == 3)
 113                 rotate_logo_one(out_logo, in_logo);
 114
 115         /* copy result back to original array */
 116         if (rotations == 1  ||  rotations == 3)
 117                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 118                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 119                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 120                                 out_logo[i * BMP_LOGO_WIDTH + j];
 121 }
 122
 123 static void enable_lvds(struct display_info_t const *dev)
 124 {
 125         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 126         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 127         int reg;
 128         s32 timeout = 100000;
 129
 130         /* set PLL5 clock */
 131         reg = readl(&ccm->analog_pll_video);
 132         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 133         writel(reg, &ccm->analog_pll_video);
 134
 135         /* set PLL5 to 232720000Hz */
 136         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 137         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 138         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 139         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 140         writel(reg, &ccm->analog_pll_video);
 141
 142         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 143                &ccm->analog_pll_video_num);
 144         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 145                &ccm->analog_pll_video_denom);
 146
 147         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 148         writel(reg, &ccm->analog_pll_video);
 149
 150         while (timeout--)
 151                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 152                         break;
 153         if (timeout < 0)
 154                 printf("Warning: video pll lock timeout!\n");
 155
 156         reg = readl(&ccm->analog_pll_video);
 157         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 158         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 159         writel(reg, &ccm->analog_pll_video);
 160
 161         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 162         reg = readl(&ccm->cs2cdr);
 163         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 164                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 165         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 166                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 167         writel(reg, &ccm->cs2cdr);
 168
 169         reg = readl(&ccm->cscmr2);
 170         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 171         writel(reg, &ccm->cscmr2);
 172
 173         reg = readl(&ccm->chsccdr);
 174         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 175                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 176         writel(reg, &ccm->chsccdr);
 177
 178         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 179               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 180               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 181               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 182               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 183               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 184               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 185         writel(reg, &iomux->gpr[2]);
 186
 187         reg = readl(&iomux->gpr[3]);
 188         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 189                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 190                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 191         writel(reg, &iomux->gpr[3]);
 192 }
 193
 194 static void enable_spi_display(struct display_info_t const *dev)
 195 {
 196         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 197         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 198         int reg;
 199         s32 timeout = 100000;
 200
 201 #if defined(CONFIG_VIDEO_BMP_LOGO)
 202         rotate_logo(3);  /* portrait display in landscape mode */
 203 #endif
 204
 205         reg = readl(&ccm->cs2cdr);
 206
 207         /* select pll 5 clock */
 208         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 209                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 210         writel(reg, &ccm->cs2cdr);
 211
 212         /* set PLL5 to 197994996Hz */
 213         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 214         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 215         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 216         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 217         writel(reg, &ccm->analog_pll_video);
 218
 219         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 220                &ccm->analog_pll_video_num);
 221         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 222                &ccm->analog_pll_video_denom);
 223
 224         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 225         writel(reg, &ccm->analog_pll_video);
 226
 227         while (timeout--)
 228                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 229                         break;
 230         if (timeout < 0)
 231                 printf("Warning: video pll lock timeout!\n");
 232
 233         reg = readl(&ccm->analog_pll_video);
 234         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 235         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 236         writel(reg, &ccm->analog_pll_video);
 237
 238         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 239         reg = readl(&ccm->cs2cdr);
 240         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 241                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 242         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 243                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 244         writel(reg, &ccm->cs2cdr);
 245
 246         reg = readl(&ccm->cscmr2);
 247         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 248         writel(reg, &ccm->cscmr2);
 249
 250         reg = readl(&ccm->chsccdr);
 251         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 252                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 253         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 254         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 255         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 256         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 257         writel(reg, &ccm->chsccdr);
 258
 259         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 260               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 261               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 262               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 263               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 264               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 265               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 266         writel(reg, &iomux->gpr[2]);
 267
 268         reg = readl(&iomux->gpr[3]);
 269         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 270                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 271                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 272         writel(reg, &iomux->gpr[3]);
 273 }
 274
 275 static void setup_display(void)
 276 {
 277         enable_ipu_clock();
 278 }
 279
 280 static void set_gpr_register(void)
 281 {
 282         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 283
 284         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 285                IOMUXC_GPR1_EXC_MON_SLVE |
 286                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 287                IOMUXC_GPR1_ACT_CS0,
 288                &iomuxc_regs->gpr[1]);
 289         writel(0x0, &iomuxc_regs->gpr[8]);
 290         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 291                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 292                &iomuxc_regs->gpr[12]);
 293 }
 294
 295 extern char __bss_start[], __bss_end[];
 296 int board_early_init_f(void)
 297 {
 298         select_ldb_di_clock_source(MXC_PLL5_CLK);
 299         set_gpr_register();
 300
 301         /*
 302          * clear bss here, so we can use spi driver
 303          * before relocation and read Environment
 304          * from spi flash.
 305          */
 306         memset(__bss_start, 0x00, __bss_end - __bss_start);
 307
 308         return 0;
 309 }
 310
 311 static void setup_one_led(char *label, int state)
 312 {
 313         struct udevice *dev;
 314         int ret;
 315
 316         ret = led_get_by_label(label, &dev);
 317         if (ret == 0)
 318                 led_set_state(dev, state);
 319 }
 320
 321 static void setup_board_gpio(void)
 322 {
 323         setup_one_led("led_ena", LEDST_ON);
 324         /* switch off Status LEDs */
 325         setup_one_led("led_yellow", LEDST_OFF);
 326         setup_one_led("led_red", LEDST_OFF);
 327         setup_one_led("led_green", LEDST_OFF);
 328         setup_one_led("led_blue", LEDST_OFF);
 329 }
 330
 331 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
 332                 " rescueReason=%d "
 333
 334 static void aristainetos_run_rescue_command(int reason)
 335 {
 336         char rescue_reason_command[80];
 337
 338         sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
 339         run_command(rescue_reason_command, 0);
 340 }
 341
 342 static int aristainetos_eeprom(void)
 343 {
 344         struct udevice *dev;
 345         int off;
 346         int ret;
 347         u8 data[0x10];
 348         u8 rescue_reason;
 349
 350         off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 351         if (off < 0) {
 352                 printf("%s: No eeprom0 path offset\n", __func__);
 353                 return off;
 354         }
 355
 356         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 357         if (ret) {
 358                 printf("%s: Could not find EEPROM\n", __func__);
 359                 return ret;
 360         }
 361
 362         ret = i2c_set_chip_offset_len(dev, 2);
 363         if (ret)
 364                 return ret;
 365
 366         ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
 367         if (ret) {
 368                 printf("%s: Could not read EEPROM\n", __func__);
 369                 return ret;
 370         }
 371
 372         if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
 373                 rescue_reason = *(uint8_t *)&data[9];
 374                 memset(&data[3], 0xff, 7);
 375                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
 376                 printf("\nBooting into Rescue System (EEPROM)\n");
 377                 aristainetos_run_rescue_command(rescue_reason);
 378                 run_command("run rescue_load_fit rescueboot", 0);
 379         } else if (strncmp((char *)data, "DeF", 3) == 0) {
 380                 memset(data, 0xff, 3);
 381                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
 382                 printf("\nClear u-boot environment (set back to defaults)\n");
 383                 run_command("run default_env; saveenv; saveenv", 0);
 384         }
 385
 386         return 0;
 387 };
 388
 389 static void aristainetos_bootmode_settings(void)
 390 {
 391         struct gpio_desc *desc;
 392         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 393         unsigned int sbmr1 = readl(&psrc->sbmr1);
 394         char *my_bootdelay;
 395         char bootmode = 0;
 396         int ret;
 397
 398         /*
 399          * Check the boot-source. If booting from NOR Flash,
 400          * disable bootdelay
 401          */
 402         ret = gpio_hog_lookup_name("bootsel0", &desc);
 403         if (!ret)
 404                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 405         ret = gpio_hog_lookup_name("bootsel1", &desc);
 406         if (!ret)
 407                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 408         ret = gpio_hog_lookup_name("bootsel2", &desc);
 409         if (!ret)
 410                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 411
 412         if (bootmode == 7) {
 413                 my_bootdelay = env_get("nor_bootdelay");
 414                 if (my_bootdelay)
 415                         env_set("bootdelay", my_bootdelay);
 416                 else
 417                         env_set("bootdelay", "-2");
 418         }
 419
 420         if (sbmr1 & 0x40) {
 421                 env_set("bootmode", "1");
 422                 printf("SD bootmode jumper set!\n");
 423         } else {
 424                 env_set("bootmode", "0");
 425         }
 426
 427         /* read out some jumper values*/
 428         ret = gpio_hog_lookup_name("env_reset", &desc);
 429         if (!ret) {
 430                 if (dm_gpio_get_value(desc)) {
 431                         printf("\nClear env (set back to defaults)\n");
 432                         run_command("run default_env; saveenv; saveenv", 0);
 433                 }
 434         }
 435         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 436         if (!ret) {
 437                 if (dm_gpio_get_value(desc)) {
 438                         aristainetos_run_rescue_command(16);
 439                         run_command("run rescue_xload_boot", 0);
 440                 }
 441         }
 442 }
 443
 444 #if defined(CONFIG_DM_PMIC_DA9063)
 445 /*
 446  * On the aristainetos2c boards the PMIC needs to be initialized,
 447  * because the Ethernet PHY uses a different regulator that is not
 448  * setup per hardware default. This does not influence the other versions
 449  * as this regulator isn't used there at all.
 450  *
 451  * Unfortunately we have not yet a interface to setup all
 452  * values we need.
 453  */
 454 static int setup_pmic_voltages(void)
 455 {
 456         struct udevice *dev;
 457         int off;
 458         int ret;
 459
 460         off = fdt_path_offset(gd->fdt_blob, "pmic0");
 461         if (off < 0) {
 462                 printf("%s: No pmic path offset\n", __func__);
 463                 return off;
 464         }
 465
 466         ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
 467         if (ret) {
 468                 printf("%s: Could not find PMIC\n", __func__);
 469                 return ret;
 470         }
 471
 472         pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
 473         pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
 474         ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
 475         if (ret < 0) {
 476                 printf("%s: error %d get register\n", __func__, ret);
 477                 return ret;
 478         }
 479         ret &= 0xf0;
 480         ret |= 0x09;
 481         pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
 482         pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
 483         pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
 484
 485         return 0;
 486 }
 487 #else
 488 static int setup_pmic_voltages(void)
 489 {
 490         return 0;
 491 }
 492 #endif
 493
 494 int board_late_init(void)
 495 {
 496         int x, y;
 497
 498         led_default_state();
 499         splash_get_pos(&x, &y);
 500         bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 501
 502         aristainetos_bootmode_settings();
 503
 504         /* eeprom work */
 505         aristainetos_eeprom();
 506
 507         /* set board_type */
 508         if (gd->board_type == BOARD_TYPE_4)
 509                 env_set("board_type", ARI_BT_4);
 510         else
 511                 env_set("board_type", ARI_BT_7);
 512
 513         if (setup_pmic_voltages())
 514                 printf("Error setup PMIC\n");
 515
 516         return 0;
 517 }
 518
 519 int dram_init(void)
 520 {
 521         gd->ram_size = imx_ddr_size();
 522
 523         return 0;
 524 }
 525
 526 struct display_info_t const displays[] = {
 527         {
 528                 .bus    = -1,
 529                 .addr   = 0,
 530                 .pixfmt = IPU_PIX_FMT_RGB24,
 531                 .detect = NULL,
 532                 .enable = enable_lvds,
 533                 .mode   = {
 534                         .name           = "lb07wv8",
 535                         .refresh        = 60,
 536                         .xres           = 800,
 537                         .yres           = 480,
 538                         .pixclock       = 30066,
 539                         .left_margin    = 88,
 540                         .right_margin   = 88,
 541                         .upper_margin   = 20,
 542                         .lower_margin   = 20,
 543                         .hsync_len      = 80,
 544                         .vsync_len      = 5,
 545                         .sync           = FB_SYNC_EXT,
 546                         .vmode          = FB_VMODE_NONINTERLACED
 547                 }
 548         }
 549 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
 550         (CONFIG_SYS_BOARD_VERSION == 3) || \
 551         (CONFIG_SYS_BOARD_VERSION == 4) || \
 552         (CONFIG_SYS_BOARD_VERSION == 5))
 553         , {
 554                 .bus    = -1,
 555                 .addr   = 0,
 556                 .pixfmt = IPU_PIX_FMT_RGB24,
 557                 .detect = NULL,
 558                 .enable = enable_spi_display,
 559                 .mode   = {
 560                         .name           = "lg4573",
 561                         .refresh        = 57,
 562                         .xres           = 480,
 563                         .yres           = 800,
 564                         .pixclock       = 37037,
 565                         .left_margin    = 59,
 566                         .right_margin   = 10,
 567                         .upper_margin   = 15,
 568                         .lower_margin   = 15,
 569                         .hsync_len      = 10,
 570                         .vsync_len      = 15,
 571                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 572                                           FB_SYNC_VERT_HIGH_ACT,
 573                         .vmode          = FB_VMODE_NONINTERLACED
 574                 }
 575         }
 576 #endif
 577 };
 578 size_t display_count = ARRAY_SIZE(displays);
 579
 580 #if defined(CONFIG_MTD_RAW_NAND)
 581 iomux_v3_cfg_t nfc_pads[] = {
 582         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 583         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 584         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 585         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 586         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 587         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 588         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 589         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 590         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 591         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 592         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 593         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 594         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 595         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 596         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 597         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 598 };
 599
 600 static void setup_gpmi_nand(void)
 601 {
 602         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 603
 604         /* config gpmi nand iomux */
 605         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 606                                          ARRAY_SIZE(nfc_pads));
 607
 608         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 609         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 610
 611         /* config gpmi and bch clock to 100 MHz */
 612         clrsetbits_le32(&mxc_ccm->cs2cdr,
 613                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 614                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 615                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 616                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 617                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 618                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 619
 620         /* enable ENFC_CLK_ROOT clock */
 621         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 622
 623         /* enable gpmi and bch clock gating */
 624         setbits_le32(&mxc_ccm->CCGR4,
 625                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 626                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 627                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 628                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 629                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 630
 631         /* enable apbh clock gating */
 632         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 633 }
 634 #else
 635 static void setup_gpmi_nand(void)
 636 {
 637 }
 638 #endif
 639
 640 int board_init(void)
 641 {
 642         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 643
 644         /* address of boot parameters */
 645         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 646
 647         setup_board_gpio();
 648         setup_gpmi_nand();
 649         setup_display();
 650
 651         /* GPIO_1 for USB_OTG_ID */
 652         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 653         return 0;
 654 }
 655
 656 int board_fit_config_name_match(const char *name)
 657 {
 658         if (gd->board_type == BOARD_TYPE_4 &&
 659             strchr(name, 0x34))
 660                 return 0;
 661
 662         if (gd->board_type == BOARD_TYPE_7 &&
 663             strchr(name, 0x37))
 664                 return 0;
 665
 666         return -1;
 667 }
 668
 669 static void do_board_detect(void)
 670 {
 671         int ret;
 672         char s[30];
 673
 674         /* default use board type 7 */
 675         gd->board_type = BOARD_TYPE_7;
 676         if (env_init())
 677                 return;
 678
 679         ret = env_get_f("panel", s, sizeof(s));
 680         if (ret < 0)
 681                 return;
 682
 683         if (!strncmp("lg4573", s, 6))
 684                 gd->board_type = BOARD_TYPE_4;
 685 }
 686
 687 #ifdef CONFIG_DTB_RESELECT
 688 int embedded_dtb_select(void)
 689 {
 690         int rescan;
 691
 692         do_board_detect();
 693         fdtdec_resetup(&rescan);
 694
 695         return 0;
 696 }
 697 #endif