board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <linux/fb.h>
  27 #include <ipu_pixfmt.h>
  28 #include <input.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <pwm.h>
  32 #include <dm/root.h>
  33 #include <env.h>
  34 #include <micrel.h>
  35 #include <spi.h>
  36 #include <video.h>
  37 #include <../drivers/video/imx/ipu.h>
  38 #if defined(CONFIG_VIDEO_BMP_LOGO)
  39         #include <bmp_logo.h>
  40 #endif
  41 #include <led.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  49                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  50
  51 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54
  55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  56
  57 #define DISP_PAD_CTRL   (0x10)
  58
  59 #define ECSPI4_CS1              IMX_GPIO_NR(5, 2)
  60
  61 #if (CONFIG_SYS_BOARD_VERSION == 2)
  62         /* 4.3 display controller */
  63         #define ECSPI1_CS0              IMX_GPIO_NR(4, 9)
  64         #define ECSPI4_CS0              IMX_GPIO_NR(3, 29)
  65 #elif (CONFIG_SYS_BOARD_VERSION == 3)
  66         #define ECSPI1_CS0              IMX_GPIO_NR(2, 30)   /* NOR flash */
  67         /* 4.3 display controller */
  68         #define ECSPI1_CS1              IMX_GPIO_NR(4, 10)
  69 #endif
  70
  71 enum {
  72         BOARD_TYPE_4 = 4,
  73         BOARD_TYPE_7 = 7,
  74 };
  75
  76 #define ARI_BT_4 "aristainetos2_4@2"
  77 #define ARI_BT_7 "aristainetos2_7@1"
  78
  79 struct i2c_pads_info i2c_pad_info3 = {
  80         .scl = {
  81                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  82                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  83                 .gp = IMX_GPIO_NR(1, 5)
  84         },
  85         .sda = {
  86                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  87                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  88                 .gp = IMX_GPIO_NR(1, 6)
  89         }
  90 };
  91
  92 struct i2c_pads_info i2c_pad_info4 = {
  93         .scl = {
  94                 .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
  95                 .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
  96                 .gp = IMX_GPIO_NR(1, 7)
  97         },
  98         .sda = {
  99                 .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
 100                 .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
 101                 .gp = IMX_GPIO_NR(1, 8)
 102         }
 103 };
 104
 105 iomux_v3_cfg_t const enet_pads[] = {
 106         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 107         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 108         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 109         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 110         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 111         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 112         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 113         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 114         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 115         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121 };
 122
 123 static iomux_v3_cfg_t const backlight_pads[] = {
 124         /* backlight PWM brightness control */
 125         MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 126         /* backlight enable */
 127         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 128         /* LCD power enable */
 129         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 130 };
 131
 132 static iomux_v3_cfg_t const ecspi1_pads[] = {
 133         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 134         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 135         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 136 #if (CONFIG_SYS_BOARD_VERSION == 2)
 137         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 138 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 139         MX6_PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 140         MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 141 #endif
 142 };
 143
 144 static void setup_iomux_enet(void)
 145 {
 146         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 147 }
 148
 149 #if (CONFIG_SYS_BOARD_VERSION == 2)
 150 iomux_v3_cfg_t const ecspi4_pads[] = {
 151         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 152         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
 153         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
 154         MX6_PAD_EIM_A25__GPIO5_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL),
 155         MX6_PAD_EIM_D29__GPIO3_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 156 };
 157 #endif
 158
 159 static iomux_v3_cfg_t const display_pads[] = {
 160         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
 161         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 162         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 163         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 164         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 165         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 166         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 167         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 168         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 169         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 170         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 171         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 172         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 173         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 174         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 175         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 176         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 177         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 178         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 179         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 180         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 181         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 182         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 183         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 184         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 185         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 186         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 187         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 188 };
 189
 190 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 191 {
 192         if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 193 #if (CONFIG_SYS_BOARD_VERSION == 2)
 194                 return IMX_GPIO_NR(5, 2);
 195
 196         if (bus == 0 && cs == 0)
 197                 return IMX_GPIO_NR(4, 9);
 198 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 199                 return ECSPI1_CS0;
 200
 201         if (bus == 0 && cs == 1)
 202                 return ECSPI1_CS1;
 203 #endif
 204         return -1;
 205 }
 206
 207 static void setup_spi(void)
 208 {
 209         int i;
 210
 211         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 212
 213 #if (CONFIG_SYS_BOARD_VERSION == 2)
 214         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
 215 #endif
 216
 217         for (i = 0; i < 4; i++)
 218                 enable_spi_clk(true, i);
 219
 220         gpio_request(ECSPI1_CS0, "spi1_cs0");
 221         gpio_direction_output(ECSPI1_CS0, 1);
 222 #if (CONFIG_SYS_BOARD_VERSION == 2)
 223         gpio_request(ECSPI4_CS1, "spi4_cs1");
 224         gpio_direction_output(ECSPI4_CS1, 0);
 225         /* set cs0 to high (second device on spi bus #4) */
 226         gpio_request(ECSPI4_CS0, "spi4_cs0");
 227         gpio_direction_output(ECSPI4_CS0, 1);
 228 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 229         gpio_request(ECSPI1_CS1, "spi1_cs1");
 230         gpio_direction_output(ECSPI1_CS1, 1);
 231 #endif
 232 }
 233
 234 int board_phy_config(struct phy_device *phydev)
 235 {
 236         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 237         ksz9031_phy_extended_write(phydev, 0x02,
 238                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 239                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 240         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 241         ksz9031_phy_extended_write(phydev, 0x02,
 242                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 243                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 244         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
 245         ksz9031_phy_extended_write(phydev, 0x02,
 246                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 247                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 248         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 249         ksz9031_phy_extended_write(phydev, 0x02,
 250                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 251                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 252
 253         if (phydev->drv->config)
 254                 phydev->drv->config(phydev);
 255
 256         return 0;
 257 }
 258
 259 int board_eth_init(bd_t *bis)
 260 {
 261         setup_iomux_enet();
 262         return cpu_eth_init(bis);
 263 }
 264
 265 static int rotate_logo_one(unsigned char *out, unsigned char *in)
 266 {
 267         int   i, j;
 268
 269         for (i = 0; i < BMP_LOGO_WIDTH; i++)
 270                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 271                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
 272                         in[i * BMP_LOGO_WIDTH + j];
 273         return 0;
 274 }
 275
 276 /*
 277  * Rotate the BMP_LOGO (only)
 278  * Will only work, if the logo is square, as
 279  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
 280  */
 281 void rotate_logo(int rotations)
 282 {
 283         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
 284         unsigned char *in_logo;
 285         int   i, j;
 286
 287         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 288                 return;
 289
 290         in_logo = bmp_logo_bitmap;
 291
 292         /* one 90 degree rotation */
 293         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 294                 rotate_logo_one(out_logo, in_logo);
 295
 296         /* second 90 degree rotation */
 297         if (rotations == 2  ||  rotations == 3)
 298                 rotate_logo_one(in_logo, out_logo);
 299
 300         /* third 90 degree rotation */
 301         if (rotations == 3)
 302                 rotate_logo_one(out_logo, in_logo);
 303
 304         /* copy result back to original array */
 305         if (rotations == 1  ||  rotations == 3)
 306                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 307                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 308                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 309                                 out_logo[i * BMP_LOGO_WIDTH + j];
 310 }
 311
 312 static void enable_display_power(void)
 313 {
 314         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 315                                          ARRAY_SIZE(backlight_pads));
 316
 317         /* backlight enable */
 318         gpio_request(IMX_GPIO_NR(6, 31), "backlight");
 319         gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
 320         gpio_free(IMX_GPIO_NR(6, 31));
 321         /* LCD power enable */
 322         gpio_request(IMX_GPIO_NR(6, 15), "LCD_power_enable");
 323         gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
 324         gpio_free(IMX_GPIO_NR(6, 15));
 325
 326         /* enable backlight PWM 1 */
 327         if (pwm_init(0, 0, 0))
 328                 goto error;
 329         /* duty cycle 500ns, period: 3000ns */
 330         if (pwm_config(0, 50000, 300000))
 331                 goto error;
 332         if (pwm_enable(0))
 333                 goto error;
 334         return;
 335
 336 error:
 337         puts("error init pwm for backlight\n");
 338 }
 339
 340 static void enable_lvds(struct display_info_t const *dev)
 341 {
 342         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 343         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 344         int reg;
 345         s32 timeout = 100000;
 346
 347         /* set PLL5 clock */
 348         reg = readl(&ccm->analog_pll_video);
 349         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 350         writel(reg, &ccm->analog_pll_video);
 351
 352         /* set PLL5 to 232720000Hz */
 353         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 354         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 355         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 356         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 357         writel(reg, &ccm->analog_pll_video);
 358
 359         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 360                &ccm->analog_pll_video_num);
 361         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 362                &ccm->analog_pll_video_denom);
 363
 364         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 365         writel(reg, &ccm->analog_pll_video);
 366
 367         while (timeout--)
 368                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 369                         break;
 370         if (timeout < 0)
 371                 printf("Warning: video pll lock timeout!\n");
 372
 373         reg = readl(&ccm->analog_pll_video);
 374         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 375         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 376         writel(reg, &ccm->analog_pll_video);
 377
 378         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 379         reg = readl(&ccm->cs2cdr);
 380         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 381                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 382         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 383                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 384         writel(reg, &ccm->cs2cdr);
 385
 386         reg = readl(&ccm->cscmr2);
 387         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 388         writel(reg, &ccm->cscmr2);
 389
 390         reg = readl(&ccm->chsccdr);
 391         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 392                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 393         writel(reg, &ccm->chsccdr);
 394
 395         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 396               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 397               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 398               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 399               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 400               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 401               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 402         writel(reg, &iomux->gpr[2]);
 403
 404         reg = readl(&iomux->gpr[3]);
 405         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 406                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 407                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 408         writel(reg, &iomux->gpr[3]);
 409 }
 410
 411 static void enable_spi_display(struct display_info_t const *dev)
 412 {
 413         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 414         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 415         int reg;
 416         s32 timeout = 100000;
 417
 418 #if defined(CONFIG_VIDEO_BMP_LOGO)
 419         rotate_logo(3);  /* portrait display in landscape mode */
 420 #endif
 421
 422         /*
 423          * set ldb clock to 28341000 Hz calculated through the formula:
 424          * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
 425          * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
 426          * see:
 427          * https://community.freescale.com/thread/308170
 428          */
 429         ipu_set_ldb_clock(28341000);
 430
 431         reg = readl(&ccm->cs2cdr);
 432
 433         /* select pll 5 clock */
 434         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 435                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 436         writel(reg, &ccm->cs2cdr);
 437
 438         /* set PLL5 to 197994996Hz */
 439         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 440         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 441         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 442         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 443         writel(reg, &ccm->analog_pll_video);
 444
 445         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 446                &ccm->analog_pll_video_num);
 447         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 448                &ccm->analog_pll_video_denom);
 449
 450         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 451         writel(reg, &ccm->analog_pll_video);
 452
 453         while (timeout--)
 454                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 455                         break;
 456         if (timeout < 0)
 457                 printf("Warning: video pll lock timeout!\n");
 458
 459         reg = readl(&ccm->analog_pll_video);
 460         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 461         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 462         writel(reg, &ccm->analog_pll_video);
 463
 464         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 465         reg = readl(&ccm->cs2cdr);
 466         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 467                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 468         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 469                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 470         writel(reg, &ccm->cs2cdr);
 471
 472         reg = readl(&ccm->cscmr2);
 473         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 474         writel(reg, &ccm->cscmr2);
 475
 476         reg = readl(&ccm->chsccdr);
 477         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 478                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 479         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 480         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 481         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 482         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 483         writel(reg, &ccm->chsccdr);
 484
 485         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 486               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 487               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 488               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 489               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 490               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 491               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 492         writel(reg, &iomux->gpr[2]);
 493
 494         reg = readl(&iomux->gpr[3]);
 495         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 496                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 497                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 498         writel(reg, &iomux->gpr[3]);
 499
 500         imx_iomux_v3_setup_multiple_pads(display_pads,
 501                                          ARRAY_SIZE(display_pads));
 502 }
 503
 504 static void setup_display(void)
 505 {
 506         enable_ipu_clock();
 507         enable_display_power();
 508 }
 509
 510 static void set_gpr_register(void)
 511 {
 512         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 513
 514         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 515                IOMUXC_GPR1_EXC_MON_SLVE |
 516                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 517                IOMUXC_GPR1_ACT_CS0,
 518                &iomuxc_regs->gpr[1]);
 519         writel(0x0, &iomuxc_regs->gpr[8]);
 520         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 521                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 522                &iomuxc_regs->gpr[12]);
 523 }
 524
 525 extern char __bss_start[], __bss_end[];
 526 int board_early_init_f(void)
 527 {
 528         setup_display();
 529         set_gpr_register();
 530
 531         /*
 532          * clear bss here, so we can use spi driver
 533          * before relocation and read Environment
 534          * from spi flash.
 535          */
 536         memset(__bss_start, 0x00, __bss_end - __bss_start);
 537
 538         return 0;
 539 }
 540
 541 static void setup_i2c4(void)
 542 {
 543         setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 544                   &i2c_pad_info4);
 545 }
 546
 547 static void setup_one_led(char *label, int state)
 548 {
 549         struct udevice *dev;
 550         int ret;
 551
 552         ret = led_get_by_label(label, &dev);
 553         if (ret == 0)
 554                 led_set_state(dev, state);
 555 }
 556
 557 static void setup_board_gpio(void)
 558 {
 559         setup_one_led("led_ena", LEDST_ON);
 560         /* switch off Status LEDs */
 561         setup_one_led("led_yellow", LEDST_OFF);
 562         setup_one_led("led_red", LEDST_OFF);
 563         setup_one_led("led_green", LEDST_OFF);
 564         setup_one_led("led_blue", LEDST_OFF);
 565 }
 566
 567 static void setup_board_spi(void)
 568 {
 569         /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
 570         gpio_request(IMX_GPIO_NR(6, 6), "spi_ena");
 571         gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
 572 }
 573
 574 int board_late_init(void)
 575 {
 576         char *my_bootdelay;
 577         char bootmode = 0;
 578         char const *panel = env_get("panel");
 579         struct gpio_desc *desc;
 580         int ret;
 581
 582         led_default_state();
 583         /*
 584          * Check the boot-source. If booting from NOR Flash,
 585          * disable bootdelay
 586          */
 587         desc = gpio_hog_lookup_name("bootsel0");
 588         if (desc)
 589                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 590         desc = gpio_hog_lookup_name("bootsel1");
 591         if (desc)
 592                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 593         desc = gpio_hog_lookup_name("bootsel2");
 594         if (desc)
 595                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 596
 597         if (bootmode == 7) {
 598                 my_bootdelay = env_get("nor_bootdelay");
 599                 if (my_bootdelay != NULL)
 600                         env_set("bootdelay", my_bootdelay);
 601                 else
 602                         env_set("bootdelay", "-2");
 603         }
 604
 605         /* read out some jumper values*/
 606         ret = gpio_hog_lookup_name("env_reset", &desc);
 607         if (!ret) {
 608                 if (dm_gpio_get_value(desc)) {
 609                         printf("\nClear env (set back to defaults)\n");
 610                         run_command("run default_env; saveenv; saveenv", 0);
 611                 }
 612         }
 613         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 614         if (!ret) {
 615                 if (dm_gpio_get_value(desc)) {
 616                         aristainetos_run_rescue_command(16);
 617                         run_command("run rescue_xload_boot", 0);
 618                 }
 619         }
 620
 621         /* if we have the lg panel, we can initialze it now */
 622         if (panel)
 623                 if (!strcmp(panel, displays[1].mode.name))
 624                         lg4573_spi_startup(CONFIG_LG4573_BUS,
 625                                            CONFIG_LG4573_CS,
 626                                            10000000, SPI_MODE_0);
 627
 628         /* set board_type */
 629         if (gd->board_type == BOARD_TYPE_4)
 630                 env_set("board_type", ARI_BT_4);
 631         else
 632                 env_set("board_type", ARI_BT_7);
 633
 634         return 0;
 635 }
 636
 637 struct i2c_pads_info i2c_pad_info1 = {
 638         .scl = {
 639                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
 640                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 641                 .gp = IMX_GPIO_NR(5, 27)
 642         },
 643         .sda = {
 644                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
 645                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 646                 .gp = IMX_GPIO_NR(5, 26)
 647         }
 648 };
 649
 650 struct i2c_pads_info i2c_pad_info2 = {
 651         .scl = {
 652                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 653                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 654                 .gp = IMX_GPIO_NR(4, 12)
 655         },
 656         .sda = {
 657                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 658                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 659                 .gp = IMX_GPIO_NR(4, 13)
 660         }
 661 };
 662
 663 int dram_init(void)
 664 {
 665         gd->ram_size = imx_ddr_size();
 666
 667         return 0;
 668 }
 669
 670 struct display_info_t const displays[] = {
 671         {
 672                 .bus    = -1,
 673                 .addr   = 0,
 674                 .pixfmt = IPU_PIX_FMT_RGB24,
 675                 .detect = NULL,
 676                 .enable = enable_lvds,
 677                 .mode   = {
 678                         .name           = "lb07wv8",
 679                         .refresh        = 60,
 680                         .xres           = 800,
 681                         .yres           = 480,
 682                         .pixclock       = 30066,
 683                         .left_margin    = 88,
 684                         .right_margin   = 88,
 685                         .upper_margin   = 20,
 686                         .lower_margin   = 20,
 687                         .hsync_len      = 80,
 688                         .vsync_len      = 5,
 689                         .sync           = FB_SYNC_EXT,
 690                         .vmode          = FB_VMODE_NONINTERLACED
 691                 }
 692         }
 693 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
 694         , {
 695                 .bus    = -1,
 696                 .addr   = 0,
 697                 .pixfmt = IPU_PIX_FMT_RGB24,
 698                 .detect = NULL,
 699                 .enable = enable_spi_display,
 700                 .mode   = {
 701                         .name           = "lg4573",
 702                         .refresh        = 57,
 703                         .xres           = 480,
 704                         .yres           = 800,
 705                         .pixclock       = 37037,
 706                         .left_margin    = 59,
 707                         .right_margin   = 10,
 708                         .upper_margin   = 15,
 709                         .lower_margin   = 15,
 710                         .hsync_len      = 10,
 711                         .vsync_len      = 15,
 712                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 713                                           FB_SYNC_VERT_HIGH_ACT,
 714                         .vmode          = FB_VMODE_NONINTERLACED
 715                 }
 716         }
 717 #endif
 718 };
 719 size_t display_count = ARRAY_SIZE(displays);
 720
 721 /* no console on this board */
 722 int board_cfb_skip(void)
 723 {
 724         return 1;
 725 }
 726
 727 iomux_v3_cfg_t nfc_pads[] = {
 728         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 729         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 730         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 731         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 732         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 733         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 734         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 735         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 736         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 737         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 738         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 739         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 740         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 741         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 742         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 743         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 744 };
 745
 746 static void setup_gpmi_nand(void)
 747 {
 748         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 749
 750         /* config gpmi nand iomux */
 751         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 752                                          ARRAY_SIZE(nfc_pads));
 753
 754         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 755         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 756
 757         /* config gpmi and bch clock to 100 MHz */
 758         clrsetbits_le32(&mxc_ccm->cs2cdr,
 759                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 760                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 761                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 762                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 763                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 764                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 765
 766         /* enable ENFC_CLK_ROOT clock */
 767         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 768
 769         /* enable gpmi and bch clock gating */
 770         setbits_le32(&mxc_ccm->CCGR4,
 771                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 772                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 773                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 774                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 775                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 776
 777         /* enable apbh clock gating */
 778         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 779 }
 780
 781 int board_init(void)
 782 {
 783         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 784
 785         /* address of boot parameters */
 786         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 787
 788         setup_spi();
 789
 790         setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 791                   &i2c_pad_info1);
 792         setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 793                   &i2c_pad_info2);
 794         setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 795                   &i2c_pad_info3);
 796         setup_i2c4();
 797
 798         /* SPI NOR Flash read only */
 799         gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
 800         gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
 801         gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
 802
 803         setup_board_gpio();
 804         setup_gpmi_nand();
 805         setup_board_spi();
 806
 807         /* GPIO_1 for USB_OTG_ID */
 808         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 809         return 0;
 810 }
 811
 812 int checkboard(void)
 813 {
 814         printf("Board: %s\n", CONFIG_BOARDNAME);
 815         return 0;
 816 }
 817
 818 int board_fit_config_name_match(const char *name)
 819 {
 820         if (gd->board_type == BOARD_TYPE_4 &&
 821             strchr(name, 0x34))
 822                 return 0;
 823
 824         if (gd->board_type == BOARD_TYPE_7 &&
 825             strchr(name, 0x37))
 826                 return 0;
 827
 828         return -1;
 829 }
 830
 831 static void do_board_detect(void)
 832 {
 833         int ret;
 834         char s[30];
 835
 836         /* default use board type 7 */
 837         gd->board_type = BOARD_TYPE_7;
 838         if (env_init())
 839                 return;
 840
 841         ret = env_get_f("panel", s, sizeof(s));
 842         if (ret < 0)
 843                 return;
 844
 845         if (!strncmp("lg4573", s, 6))
 846                 gd->board_type = BOARD_TYPE_4;
 847 }
 848
 849 #ifdef CONFIG_DTB_RESELECT
 850 int embedded_dtb_select(void)
 851 {
 852         int rescan;
 853
 854         do_board_detect();
 855         fdtdec_resetup(&rescan);
 856
 857         return 0;
 858 }
 859 #endif