board/aristainetos/aristainetos.c

   1 /*
   2  * (C) Copyright 2014
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * Based on:
   6  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   7  *
   8  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <linux/errno.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/mxc_i2c.h>
  22 #include <asm/mach-imx/video.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <linux/fb.h>
  30 #include <ipu_pixfmt.h>
  31 #include <input.h>
  32 #include <asm/io.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <pwm.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  39         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  40         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  41
  42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  43         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  44         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  45
  46 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  47         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  48
  49 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  50                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  51
  52 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  54         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  55
  56 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  57
  58 #define DISP_PAD_CTRL   (0x10)
  59
  60 #define ECSPI4_CS1              IMX_GPIO_NR(5, 2)
  61
  62 #if (CONFIG_SYS_BOARD_VERSION == 1)
  63 #include "./aristainetos-v1.c"
  64 #elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
  65 #include "./aristainetos-v2.c"
  66 #endif
  67
  68
  69 struct i2c_pads_info i2c_pad_info1 = {
  70         .scl = {
  71                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
  72                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  73                 .gp = IMX_GPIO_NR(5, 27)
  74         },
  75         .sda = {
  76                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  77                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  78                 .gp = IMX_GPIO_NR(5, 26)
  79         }
  80 };
  81
  82 struct i2c_pads_info i2c_pad_info2 = {
  83         .scl = {
  84                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  85                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  86                 .gp = IMX_GPIO_NR(4, 12)
  87         },
  88         .sda = {
  89                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  90                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  91                 .gp = IMX_GPIO_NR(4, 13)
  92         }
  93 };
  94
  95 iomux_v3_cfg_t const usdhc1_pads[] = {
  96         MX6_PAD_SD1_CLK__SD1_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97         MX6_PAD_SD1_CMD__SD1_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD1_DAT0__SD1_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD1_DAT1__SD1_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD1_DAT2__SD1_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD1_DAT3__SD1_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102 };
 103
 104 int dram_init(void)
 105 {
 106         gd->ram_size = imx_ddr_size();
 107
 108         return 0;
 109 }
 110
 111 #ifdef CONFIG_FSL_ESDHC
 112 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 113         {USDHC1_BASE_ADDR},
 114         {USDHC2_BASE_ADDR},
 115 };
 116
 117 int board_mmc_getcd(struct mmc *mmc)
 118 {
 119         return 1;
 120 }
 121
 122 int board_mmc_init(bd_t *bis)
 123 {
 124         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 125         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 126 #if (CONFIG_SYS_BOARD_VERSION == 2)
 127         /*
 128          * usdhc2 has a levelshifter on the carrier board Rev. DV1,
 129          * that will automatically detect the driving direction.
 130          * During initialisation this isn't working correctly,
 131          * which causes DAT3 to be driven low towards the SD-card.
 132          * This causes a SD-card enetring the SPI-Mode
 133          * and therefore getting inaccessible until next power cycle.
 134          * As workaround we drive the DAT3 line as GPIO and set it high.
 135          * This makes usdhc2 unusable in u-boot, but works for the
 136          * initialisation in Linux
 137          */
 138         imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
 139                                MUX_PAD_CTRL(NO_PAD_CTRL));
 140         gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
 141 #endif
 142         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 143 }
 144 #endif
 145
 146 /*
 147  * Do not overwrite the console
 148  * Use always serial for U-Boot console
 149  */
 150 int overwrite_console(void)
 151 {
 152         return 1;
 153 }
 154
 155 struct display_info_t const displays[] = {
 156         {
 157                 .bus    = -1,
 158                 .addr   = 0,
 159                 .pixfmt = IPU_PIX_FMT_RGB24,
 160                 .detect = NULL,
 161                 .enable = enable_lvds,
 162                 .mode   = {
 163                         .name           = "lb07wv8",
 164                         .refresh        = 60,
 165                         .xres           = 800,
 166                         .yres           = 480,
 167                         .pixclock       = 30066,
 168                         .left_margin    = 88,
 169                         .right_margin   = 88,
 170                         .upper_margin   = 20,
 171                         .lower_margin   = 20,
 172                         .hsync_len      = 80,
 173                         .vsync_len      = 5,
 174                         .sync           = FB_SYNC_EXT,
 175                         .vmode          = FB_VMODE_NONINTERLACED
 176                 }
 177         }
 178 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
 179         , {
 180                 .bus    = -1,
 181                 .addr   = 0,
 182                 .pixfmt = IPU_PIX_FMT_RGB24,
 183                 .detect = NULL,
 184                 .enable = enable_spi_display,
 185                 .mode   = {
 186                         .name           = "lg4573",
 187                         .refresh        = 57,
 188                         .xres           = 480,
 189                         .yres           = 800,
 190                         .pixclock       = 37037,
 191                         .left_margin    = 59,
 192                         .right_margin   = 10,
 193                         .upper_margin   = 15,
 194                         .lower_margin   = 15,
 195                         .hsync_len      = 10,
 196                         .vsync_len      = 15,
 197                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 198                                           FB_SYNC_VERT_HIGH_ACT,
 199                         .vmode          = FB_VMODE_NONINTERLACED
 200                 }
 201         }
 202 #endif
 203 };
 204 size_t display_count = ARRAY_SIZE(displays);
 205
 206 /* no console on this board */
 207 int board_cfb_skip(void)
 208 {
 209         return 1;
 210 }
 211
 212 iomux_v3_cfg_t nfc_pads[] = {
 213         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 214         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 215         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 216         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 217         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 218         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 219         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 220         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 221         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 222         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 223         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 224         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 225         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 226         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 227         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 228         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 229 };
 230
 231 static void setup_gpmi_nand(void)
 232 {
 233         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 234
 235         /* config gpmi nand iomux */
 236         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 237                                          ARRAY_SIZE(nfc_pads));
 238
 239         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 240         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 241
 242         /* config gpmi and bch clock to 100 MHz */
 243         clrsetbits_le32(&mxc_ccm->cs2cdr,
 244                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 245                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 246                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 247                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 248                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 249                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 250
 251         /* enable ENFC_CLK_ROOT clock */
 252         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 253
 254         /* enable gpmi and bch clock gating */
 255         setbits_le32(&mxc_ccm->CCGR4,
 256                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 257                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 258                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 259                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 260                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 261
 262         /* enable apbh clock gating */
 263         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 264 }
 265
 266 int board_init(void)
 267 {
 268         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 269
 270         /* address of boot parameters */
 271         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 272
 273         setup_spi();
 274
 275         setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 276                   &i2c_pad_info1);
 277         setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 278                   &i2c_pad_info2);
 279         setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 280                   &i2c_pad_info3);
 281         setup_i2c4();
 282
 283         /* SPI NOR Flash read only */
 284         gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
 285         gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
 286         gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
 287
 288         setup_board_gpio();
 289         setup_gpmi_nand();
 290         setup_board_spi();
 291
 292         /* GPIO_1 for USB_OTG_ID */
 293         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 294         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 295         return 0;
 296 }
 297
 298 int checkboard(void)
 299 {
 300         printf("Board: %s\n", CONFIG_BOARDNAME);
 301         return 0;
 302 }
 303
 304 #ifdef CONFIG_USB_EHCI_MX6
 305 int board_ehci_hcd_init(int port)
 306 {
 307         int ret;
 308
 309         ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
 310         if (!ret)
 311                 gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
 312         ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
 313         if (!ret)
 314                 gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
 315         return 0;
 316 }
 317
 318 int board_ehci_power(int port, int on)
 319 {
 320         if (port)
 321                 gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
 322         else
 323                 gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
 324         return 0;
 325 }
 326 #endif