1 // SPDX-License-Identifier: GPL-2.0+
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * Author: Fabio Estevam <fabio.estevam@freescale.com>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <linux/errno.h>
18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/mxc_i2c.h>
21 #include <asm/mach-imx/video.h>
22 #include <asm/arch/crm_regs.h>
24 #include <asm/arch/sys_proto.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
40 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
42 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
49 #define ARI_BT_4 "aristainetos2_4@2"
50 #define ARI_BT_7 "aristainetos2_7@1"
52 struct i2c_pads_info i2c_pad_info3 = {
54 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
55 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
56 .gp = IMX_GPIO_NR(1, 5)
59 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
60 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
61 .gp = IMX_GPIO_NR(1, 6)
65 struct i2c_pads_info i2c_pad_info4 = {
67 .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
68 .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
69 .gp = IMX_GPIO_NR(1, 7)
72 .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
73 .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
74 .gp = IMX_GPIO_NR(1, 8)
78 static iomux_v3_cfg_t const backlight_pads[] = {
79 /* backlight PWM brightness control */
80 MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
81 /* backlight enable */
82 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
83 /* LCD power enable */
84 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
87 int board_phy_config(struct phy_device *phydev)
89 /* control data pad skew - devaddr = 0x02, register = 0x04 */
90 ksz9031_phy_extended_write(phydev, 0x02,
91 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
92 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
93 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
94 ksz9031_phy_extended_write(phydev, 0x02,
95 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
96 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
97 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
98 ksz9031_phy_extended_write(phydev, 0x02,
99 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
100 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
101 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
102 ksz9031_phy_extended_write(phydev, 0x02,
103 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
104 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
106 if (phydev->drv->config)
107 phydev->drv->config(phydev);
112 static int rotate_logo_one(unsigned char *out, unsigned char *in)
116 for (i = 0; i < BMP_LOGO_WIDTH; i++)
117 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
118 out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
119 in[i * BMP_LOGO_WIDTH + j];
124 * Rotate the BMP_LOGO (only)
125 * Will only work, if the logo is square, as
126 * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
128 void rotate_logo(int rotations)
130 unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
131 struct bmp_header *header;
132 unsigned char *in_logo;
135 if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
138 header = (struct bmp_header *)bmp_logo_bitmap;
139 in_logo = bmp_logo_bitmap + header->data_offset;
141 /* one 90 degree rotation */
142 if (rotations == 1 || rotations == 2 || rotations == 3)
143 rotate_logo_one(out_logo, in_logo);
145 /* second 90 degree rotation */
146 if (rotations == 2 || rotations == 3)
147 rotate_logo_one(in_logo, out_logo);
149 /* third 90 degree rotation */
151 rotate_logo_one(out_logo, in_logo);
153 /* copy result back to original array */
154 if (rotations == 1 || rotations == 3)
155 for (i = 0; i < BMP_LOGO_WIDTH; i++)
156 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
157 in_logo[i * BMP_LOGO_WIDTH + j] =
158 out_logo[i * BMP_LOGO_WIDTH + j];
161 static void enable_lvds(struct display_info_t const *dev)
163 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
164 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
166 s32 timeout = 100000;
169 reg = readl(&ccm->analog_pll_video);
170 reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
171 writel(reg, &ccm->analog_pll_video);
173 /* set PLL5 to 232720000Hz */
174 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
175 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
176 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
177 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
178 writel(reg, &ccm->analog_pll_video);
180 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
181 &ccm->analog_pll_video_num);
182 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
183 &ccm->analog_pll_video_denom);
185 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
186 writel(reg, &ccm->analog_pll_video);
189 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
192 printf("Warning: video pll lock timeout!\n");
194 reg = readl(&ccm->analog_pll_video);
195 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
196 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
197 writel(reg, &ccm->analog_pll_video);
199 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
200 reg = readl(&ccm->cs2cdr);
201 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
202 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
203 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
204 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
205 writel(reg, &ccm->cs2cdr);
207 reg = readl(&ccm->cscmr2);
208 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
209 writel(reg, &ccm->cscmr2);
211 reg = readl(&ccm->chsccdr);
212 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
213 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
214 writel(reg, &ccm->chsccdr);
216 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
217 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
218 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
219 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
220 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
221 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
222 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
223 writel(reg, &iomux->gpr[2]);
225 reg = readl(&iomux->gpr[3]);
226 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
227 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
228 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
229 writel(reg, &iomux->gpr[3]);
232 static void enable_spi_display(struct display_info_t const *dev)
234 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
235 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
237 s32 timeout = 100000;
239 #if defined(CONFIG_VIDEO_BMP_LOGO)
240 rotate_logo(3); /* portrait display in landscape mode */
243 reg = readl(&ccm->cs2cdr);
245 /* select pll 5 clock */
246 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
247 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
248 writel(reg, &ccm->cs2cdr);
250 /* set PLL5 to 197994996Hz */
251 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
252 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
253 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
254 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
255 writel(reg, &ccm->analog_pll_video);
257 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
258 &ccm->analog_pll_video_num);
259 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
260 &ccm->analog_pll_video_denom);
262 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
263 writel(reg, &ccm->analog_pll_video);
266 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
269 printf("Warning: video pll lock timeout!\n");
271 reg = readl(&ccm->analog_pll_video);
272 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
273 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
274 writel(reg, &ccm->analog_pll_video);
276 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
277 reg = readl(&ccm->cs2cdr);
278 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
279 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
280 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
281 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
282 writel(reg, &ccm->cs2cdr);
284 reg = readl(&ccm->cscmr2);
285 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
286 writel(reg, &ccm->cscmr2);
288 reg = readl(&ccm->chsccdr);
289 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
290 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
291 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
292 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
293 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
294 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
295 writel(reg, &ccm->chsccdr);
297 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
298 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
299 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
300 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
301 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
302 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
303 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
304 writel(reg, &iomux->gpr[2]);
306 reg = readl(&iomux->gpr[3]);
307 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
308 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
309 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
310 writel(reg, &iomux->gpr[3]);
313 static void setup_display(void)
318 static void set_gpr_register(void)
320 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
322 writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
323 IOMUXC_GPR1_EXC_MON_SLVE |
324 (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
326 &iomuxc_regs->gpr[1]);
327 writel(0x0, &iomuxc_regs->gpr[8]);
328 writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
329 IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
330 &iomuxc_regs->gpr[12]);
333 extern char __bss_start[], __bss_end[];
334 int board_early_init_f(void)
336 select_ldb_di_clock_source(MXC_PLL5_CLK);
340 * clear bss here, so we can use spi driver
341 * before relocation and read Environment
344 memset(__bss_start, 0x00, __bss_end - __bss_start);
349 static void setup_i2c4(void)
351 setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
355 static void setup_one_led(char *label, int state)
360 ret = led_get_by_label(label, &dev);
362 led_set_state(dev, state);
365 static void setup_board_gpio(void)
367 setup_one_led("led_ena", LEDST_ON);
368 /* switch off Status LEDs */
369 setup_one_led("led_yellow", LEDST_OFF);
370 setup_one_led("led_red", LEDST_OFF);
371 setup_one_led("led_green", LEDST_OFF);
372 setup_one_led("led_blue", LEDST_OFF);
375 int board_late_init(void)
379 struct gpio_desc *desc;
384 splash_get_pos(&x, &y);
385 bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
387 * Check the boot-source. If booting from NOR Flash,
390 desc = gpio_hog_lookup_name("bootsel0");
392 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
393 desc = gpio_hog_lookup_name("bootsel1");
395 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
396 desc = gpio_hog_lookup_name("bootsel2");
398 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
401 my_bootdelay = env_get("nor_bootdelay");
402 if (my_bootdelay != NULL)
403 env_set("bootdelay", my_bootdelay);
405 env_set("bootdelay", "-2");
408 /* read out some jumper values*/
409 ret = gpio_hog_lookup_name("env_reset", &desc);
411 if (dm_gpio_get_value(desc)) {
412 printf("\nClear env (set back to defaults)\n");
413 run_command("run default_env; saveenv; saveenv", 0);
416 ret = gpio_hog_lookup_name("boot_rescue", &desc);
418 if (dm_gpio_get_value(desc)) {
419 aristainetos_run_rescue_command(16);
420 run_command("run rescue_xload_boot", 0);
425 if (gd->board_type == BOARD_TYPE_4)
426 env_set("board_type", ARI_BT_4);
428 env_set("board_type", ARI_BT_7);
433 struct i2c_pads_info i2c_pad_info1 = {
435 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
436 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
437 .gp = IMX_GPIO_NR(5, 27)
440 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
441 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
442 .gp = IMX_GPIO_NR(5, 26)
446 struct i2c_pads_info i2c_pad_info2 = {
448 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
449 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
450 .gp = IMX_GPIO_NR(4, 12)
453 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
454 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
455 .gp = IMX_GPIO_NR(4, 13)
461 gd->ram_size = imx_ddr_size();
466 struct display_info_t const displays[] = {
470 .pixfmt = IPU_PIX_FMT_RGB24,
472 .enable = enable_lvds,
486 .vmode = FB_VMODE_NONINTERLACED
489 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
493 .pixfmt = IPU_PIX_FMT_RGB24,
495 .enable = enable_spi_display,
508 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
509 FB_SYNC_VERT_HIGH_ACT,
510 .vmode = FB_VMODE_NONINTERLACED
515 size_t display_count = ARRAY_SIZE(displays);
517 iomux_v3_cfg_t nfc_pads[] = {
518 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
519 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
520 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
521 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
522 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
523 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
524 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
525 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
526 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
527 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
528 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
529 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
530 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
531 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
532 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
533 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
536 static void setup_gpmi_nand(void)
538 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
540 /* config gpmi nand iomux */
541 imx_iomux_v3_setup_multiple_pads(nfc_pads,
542 ARRAY_SIZE(nfc_pads));
544 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
545 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
547 /* config gpmi and bch clock to 100 MHz */
548 clrsetbits_le32(&mxc_ccm->cs2cdr,
549 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
550 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
551 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
552 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
553 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
554 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
556 /* enable ENFC_CLK_ROOT clock */
557 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
559 /* enable gpmi and bch clock gating */
560 setbits_le32(&mxc_ccm->CCGR4,
561 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
562 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
563 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
564 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
565 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
567 /* enable apbh clock gating */
568 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
573 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
575 /* address of boot parameters */
576 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
578 setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
580 setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
582 setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
590 /* GPIO_1 for USB_OTG_ID */
591 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
597 printf("Board: %s\n", CONFIG_BOARDNAME);
601 int board_fit_config_name_match(const char *name)
603 if (gd->board_type == BOARD_TYPE_4 &&
607 if (gd->board_type == BOARD_TYPE_7 &&
614 static void do_board_detect(void)
619 /* default use board type 7 */
620 gd->board_type = BOARD_TYPE_7;
624 ret = env_get_f("panel", s, sizeof(s));
628 if (!strncmp("lg4573", s, 6))
629 gd->board_type = BOARD_TYPE_4;
632 #ifdef CONFIG_DTB_RESELECT
633 int embedded_dtb_select(void)
638 fdtdec_resetup(&rescan);