board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <miiphy.h>
  23 #include <netdev.h>
  24 #include <asm/arch/mxc_hdmi.h>
  25 #include <asm/arch/crm_regs.h>
  26 #include <linux/fb.h>
  27 #include <ipu_pixfmt.h>
  28 #include <input.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <pwm.h>
  32 #include <dm/root.h>
  33 #include <env.h>
  34 #include <micrel.h>
  35 #include <spi.h>
  36 #include <video.h>
  37 #include <../drivers/video/imx/ipu.h>
  38 #if defined(CONFIG_VIDEO_BMP_LOGO)
  39         #include <bmp_logo.h>
  40 #endif
  41 #include <led.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47
  48 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  49                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  50
  51 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  52         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  53         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  54
  55 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  56
  57 #define DISP_PAD_CTRL   (0x10)
  58
  59 #define ECSPI4_CS1              IMX_GPIO_NR(5, 2)
  60
  61 #if (CONFIG_SYS_BOARD_VERSION == 2)
  62         /* 4.3 display controller */
  63         #define ECSPI1_CS0              IMX_GPIO_NR(4, 9)
  64         #define ECSPI4_CS0              IMX_GPIO_NR(3, 29)
  65 #elif (CONFIG_SYS_BOARD_VERSION == 3)
  66         #define ECSPI1_CS0              IMX_GPIO_NR(2, 30)   /* NOR flash */
  67         /* 4.3 display controller */
  68         #define ECSPI1_CS1              IMX_GPIO_NR(4, 10)
  69 #endif
  70
  71 enum {
  72         BOARD_TYPE_4 = 4,
  73         BOARD_TYPE_7 = 7,
  74 };
  75
  76 #define ARI_BT_4 "aristainetos2_4@2"
  77 #define ARI_BT_7 "aristainetos2_7@1"
  78
  79 struct i2c_pads_info i2c_pad_info3 = {
  80         .scl = {
  81                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  82                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  83                 .gp = IMX_GPIO_NR(1, 5)
  84         },
  85         .sda = {
  86                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  87                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  88                 .gp = IMX_GPIO_NR(1, 6)
  89         }
  90 };
  91
  92 struct i2c_pads_info i2c_pad_info4 = {
  93         .scl = {
  94                 .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
  95                 .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
  96                 .gp = IMX_GPIO_NR(1, 7)
  97         },
  98         .sda = {
  99                 .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
 100                 .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
 101                 .gp = IMX_GPIO_NR(1, 8)
 102         }
 103 };
 104
 105 static iomux_v3_cfg_t const misc_pads[] = {
 106         /* USB_OTG_ID = GPIO1_24*/
 107         MX6_PAD_ENET_RX_ER__USB_OTG_ID          | MUX_PAD_CTRL(NO_PAD_CTRL),
 108         /* H1 Power enable = GPIO1_0*/
 109         MX6_PAD_GPIO_0__USB_H1_PWR              | MUX_PAD_CTRL(NO_PAD_CTRL),
 110         /* OTG Power enable = GPIO4_15*/
 111         MX6_PAD_KEY_ROW4__USB_OTG_PWR           | MUX_PAD_CTRL(NO_PAD_CTRL),
 112 };
 113
 114 iomux_v3_cfg_t const enet_pads[] = {
 115         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 116         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 117         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 125         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 126         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 127         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 128         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 129         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 130 };
 131
 132 static iomux_v3_cfg_t const backlight_pads[] = {
 133         /* backlight PWM brightness control */
 134         MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 135         /* backlight enable */
 136         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 137         /* LCD power enable */
 138         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 139 };
 140
 141 static iomux_v3_cfg_t const ecspi1_pads[] = {
 142         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 143         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 144         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 145 #if (CONFIG_SYS_BOARD_VERSION == 2)
 146         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 147 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 148         MX6_PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 149         MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 150 #endif
 151 };
 152
 153 static void setup_iomux_enet(void)
 154 {
 155         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 156 }
 157
 158 #if (CONFIG_SYS_BOARD_VERSION == 2)
 159 iomux_v3_cfg_t const ecspi4_pads[] = {
 160         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 161         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
 163         MX6_PAD_EIM_A25__GPIO5_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         MX6_PAD_EIM_D29__GPIO3_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 165 };
 166 #endif
 167
 168 static iomux_v3_cfg_t const display_pads[] = {
 169         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
 170         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 171         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 172         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 173         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 174         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 175         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 176         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 177         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 178         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 179         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 180         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 181         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 182         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 183         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 184         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 185         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 186         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 187         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 188         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 189         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 190         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 191         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 192         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 193         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 194         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 195         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 196         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 197 };
 198
 199 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 200 {
 201         if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 202 #if (CONFIG_SYS_BOARD_VERSION == 2)
 203                 return IMX_GPIO_NR(5, 2);
 204
 205         if (bus == 0 && cs == 0)
 206                 return IMX_GPIO_NR(4, 9);
 207 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 208                 return ECSPI1_CS0;
 209
 210         if (bus == 0 && cs == 1)
 211                 return ECSPI1_CS1;
 212 #endif
 213         return -1;
 214 }
 215
 216 static void setup_spi(void)
 217 {
 218         int i;
 219
 220         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 221
 222 #if (CONFIG_SYS_BOARD_VERSION == 2)
 223         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
 224 #endif
 225
 226         for (i = 0; i < 4; i++)
 227                 enable_spi_clk(true, i);
 228
 229         gpio_request(ECSPI1_CS0, "spi1_cs0");
 230         gpio_direction_output(ECSPI1_CS0, 1);
 231 #if (CONFIG_SYS_BOARD_VERSION == 2)
 232         gpio_request(ECSPI4_CS1, "spi4_cs1");
 233         gpio_direction_output(ECSPI4_CS1, 0);
 234         /* set cs0 to high (second device on spi bus #4) */
 235         gpio_request(ECSPI4_CS0, "spi4_cs0");
 236         gpio_direction_output(ECSPI4_CS0, 1);
 237 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 238         gpio_request(ECSPI1_CS1, "spi1_cs1");
 239         gpio_direction_output(ECSPI1_CS1, 1);
 240 #endif
 241 }
 242
 243 int board_phy_config(struct phy_device *phydev)
 244 {
 245         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 246         ksz9031_phy_extended_write(phydev, 0x02,
 247                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 248                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 249         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 250         ksz9031_phy_extended_write(phydev, 0x02,
 251                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 252                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 253         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
 254         ksz9031_phy_extended_write(phydev, 0x02,
 255                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 256                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 257         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 258         ksz9031_phy_extended_write(phydev, 0x02,
 259                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 260                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 261
 262         if (phydev->drv->config)
 263                 phydev->drv->config(phydev);
 264
 265         return 0;
 266 }
 267
 268 int board_eth_init(bd_t *bis)
 269 {
 270         setup_iomux_enet();
 271         return cpu_eth_init(bis);
 272 }
 273
 274 static int rotate_logo_one(unsigned char *out, unsigned char *in)
 275 {
 276         int   i, j;
 277
 278         for (i = 0; i < BMP_LOGO_WIDTH; i++)
 279                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 280                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
 281                         in[i * BMP_LOGO_WIDTH + j];
 282         return 0;
 283 }
 284
 285 /*
 286  * Rotate the BMP_LOGO (only)
 287  * Will only work, if the logo is square, as
 288  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
 289  */
 290 void rotate_logo(int rotations)
 291 {
 292         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
 293         unsigned char *in_logo;
 294         int   i, j;
 295
 296         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 297                 return;
 298
 299         in_logo = bmp_logo_bitmap;
 300
 301         /* one 90 degree rotation */
 302         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 303                 rotate_logo_one(out_logo, in_logo);
 304
 305         /* second 90 degree rotation */
 306         if (rotations == 2  ||  rotations == 3)
 307                 rotate_logo_one(in_logo, out_logo);
 308
 309         /* third 90 degree rotation */
 310         if (rotations == 3)
 311                 rotate_logo_one(out_logo, in_logo);
 312
 313         /* copy result back to original array */
 314         if (rotations == 1  ||  rotations == 3)
 315                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 316                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 317                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 318                                 out_logo[i * BMP_LOGO_WIDTH + j];
 319 }
 320
 321 static void enable_display_power(void)
 322 {
 323         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 324                                          ARRAY_SIZE(backlight_pads));
 325
 326         /* backlight enable */
 327         gpio_request(IMX_GPIO_NR(6, 31), "backlight");
 328         gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
 329         gpio_free(IMX_GPIO_NR(6, 31));
 330         /* LCD power enable */
 331         gpio_request(IMX_GPIO_NR(6, 15), "LCD_power_enable");
 332         gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
 333         gpio_free(IMX_GPIO_NR(6, 15));
 334
 335         /* enable backlight PWM 1 */
 336         if (pwm_init(0, 0, 0))
 337                 goto error;
 338         /* duty cycle 500ns, period: 3000ns */
 339         if (pwm_config(0, 50000, 300000))
 340                 goto error;
 341         if (pwm_enable(0))
 342                 goto error;
 343         return;
 344
 345 error:
 346         puts("error init pwm for backlight\n");
 347 }
 348
 349 static void enable_lvds(struct display_info_t const *dev)
 350 {
 351         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 352         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 353         int reg;
 354         s32 timeout = 100000;
 355
 356         /* set PLL5 clock */
 357         reg = readl(&ccm->analog_pll_video);
 358         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 359         writel(reg, &ccm->analog_pll_video);
 360
 361         /* set PLL5 to 232720000Hz */
 362         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 363         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 364         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 365         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 366         writel(reg, &ccm->analog_pll_video);
 367
 368         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 369                &ccm->analog_pll_video_num);
 370         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 371                &ccm->analog_pll_video_denom);
 372
 373         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 374         writel(reg, &ccm->analog_pll_video);
 375
 376         while (timeout--)
 377                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 378                         break;
 379         if (timeout < 0)
 380                 printf("Warning: video pll lock timeout!\n");
 381
 382         reg = readl(&ccm->analog_pll_video);
 383         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 384         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 385         writel(reg, &ccm->analog_pll_video);
 386
 387         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 388         reg = readl(&ccm->cs2cdr);
 389         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 390                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 391         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 392                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 393         writel(reg, &ccm->cs2cdr);
 394
 395         reg = readl(&ccm->cscmr2);
 396         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 397         writel(reg, &ccm->cscmr2);
 398
 399         reg = readl(&ccm->chsccdr);
 400         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 401                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 402         writel(reg, &ccm->chsccdr);
 403
 404         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 405               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 406               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 407               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 408               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 409               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 410               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 411         writel(reg, &iomux->gpr[2]);
 412
 413         reg = readl(&iomux->gpr[3]);
 414         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 415                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 416                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 417         writel(reg, &iomux->gpr[3]);
 418 }
 419
 420 static void enable_spi_display(struct display_info_t const *dev)
 421 {
 422         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 423         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 424         int reg;
 425         s32 timeout = 100000;
 426
 427 #if defined(CONFIG_VIDEO_BMP_LOGO)
 428         rotate_logo(3);  /* portrait display in landscape mode */
 429 #endif
 430
 431         /*
 432          * set ldb clock to 28341000 Hz calculated through the formula:
 433          * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
 434          * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
 435          * see:
 436          * https://community.freescale.com/thread/308170
 437          */
 438         ipu_set_ldb_clock(28341000);
 439
 440         reg = readl(&ccm->cs2cdr);
 441
 442         /* select pll 5 clock */
 443         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 444                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 445         writel(reg, &ccm->cs2cdr);
 446
 447         /* set PLL5 to 197994996Hz */
 448         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 449         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 450         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 451         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 452         writel(reg, &ccm->analog_pll_video);
 453
 454         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 455                &ccm->analog_pll_video_num);
 456         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 457                &ccm->analog_pll_video_denom);
 458
 459         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 460         writel(reg, &ccm->analog_pll_video);
 461
 462         while (timeout--)
 463                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 464                         break;
 465         if (timeout < 0)
 466                 printf("Warning: video pll lock timeout!\n");
 467
 468         reg = readl(&ccm->analog_pll_video);
 469         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 470         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 471         writel(reg, &ccm->analog_pll_video);
 472
 473         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 474         reg = readl(&ccm->cs2cdr);
 475         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 476                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 477         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 478                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 479         writel(reg, &ccm->cs2cdr);
 480
 481         reg = readl(&ccm->cscmr2);
 482         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 483         writel(reg, &ccm->cscmr2);
 484
 485         reg = readl(&ccm->chsccdr);
 486         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 487                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 488         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 489         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 490         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 491         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 492         writel(reg, &ccm->chsccdr);
 493
 494         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 495               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 496               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 497               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 498               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 499               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 500               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 501         writel(reg, &iomux->gpr[2]);
 502
 503         reg = readl(&iomux->gpr[3]);
 504         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 505                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 506                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 507         writel(reg, &iomux->gpr[3]);
 508
 509         imx_iomux_v3_setup_multiple_pads(display_pads,
 510                                          ARRAY_SIZE(display_pads));
 511 }
 512
 513 static void setup_display(void)
 514 {
 515         enable_ipu_clock();
 516         enable_display_power();
 517 }
 518
 519 static void set_gpr_register(void)
 520 {
 521         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 522
 523         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 524                IOMUXC_GPR1_EXC_MON_SLVE |
 525                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 526                IOMUXC_GPR1_ACT_CS0,
 527                &iomuxc_regs->gpr[1]);
 528         writel(0x0, &iomuxc_regs->gpr[8]);
 529         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 530                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 531                &iomuxc_regs->gpr[12]);
 532 }
 533
 534 extern char __bss_start[], __bss_end[];
 535 int board_early_init_f(void)
 536 {
 537         setup_display();
 538         set_gpr_register();
 539
 540         /*
 541          * clear bss here, so we can use spi driver
 542          * before relocation and read Environment
 543          * from spi flash.
 544          */
 545         memset(__bss_start, 0x00, __bss_end - __bss_start);
 546
 547         return 0;
 548 }
 549
 550 static void setup_i2c4(void)
 551 {
 552         setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 553                   &i2c_pad_info4);
 554 }
 555
 556 static void setup_one_led(char *label, int state)
 557 {
 558         struct udevice *dev;
 559         int ret;
 560
 561         ret = led_get_by_label(label, &dev);
 562         if (ret == 0)
 563                 led_set_state(dev, state);
 564 }
 565
 566 static void setup_board_gpio(void)
 567 {
 568         setup_one_led("led_ena", LEDST_ON);
 569         /* switch off Status LEDs */
 570         setup_one_led("led_yellow", LEDST_OFF);
 571         setup_one_led("led_red", LEDST_OFF);
 572         setup_one_led("led_green", LEDST_OFF);
 573         setup_one_led("led_blue", LEDST_OFF);
 574 }
 575
 576 static void setup_board_spi(void)
 577 {
 578         /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
 579         gpio_request(IMX_GPIO_NR(6, 6), "spi_ena");
 580         gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
 581 }
 582
 583 int board_late_init(void)
 584 {
 585         char *my_bootdelay;
 586         char bootmode = 0;
 587         char const *panel = env_get("panel");
 588         struct gpio_desc *desc;
 589         int ret;
 590
 591         led_default_state();
 592         /*
 593          * Check the boot-source. If booting from NOR Flash,
 594          * disable bootdelay
 595          */
 596         desc = gpio_hog_lookup_name("bootsel0");
 597         if (desc)
 598                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 599         desc = gpio_hog_lookup_name("bootsel1");
 600         if (desc)
 601                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 602         desc = gpio_hog_lookup_name("bootsel2");
 603         if (desc)
 604                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 605
 606         if (bootmode == 7) {
 607                 my_bootdelay = env_get("nor_bootdelay");
 608                 if (my_bootdelay != NULL)
 609                         env_set("bootdelay", my_bootdelay);
 610                 else
 611                         env_set("bootdelay", "-2");
 612         }
 613
 614         /* read out some jumper values*/
 615         ret = gpio_hog_lookup_name("env_reset", &desc);
 616         if (!ret) {
 617                 if (dm_gpio_get_value(desc)) {
 618                         printf("\nClear env (set back to defaults)\n");
 619                         run_command("run default_env; saveenv; saveenv", 0);
 620                 }
 621         }
 622         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 623         if (!ret) {
 624                 if (dm_gpio_get_value(desc)) {
 625                         aristainetos_run_rescue_command(16);
 626                         run_command("run rescue_xload_boot", 0);
 627                 }
 628         }
 629
 630         /* if we have the lg panel, we can initialze it now */
 631         if (panel)
 632                 if (!strcmp(panel, displays[1].mode.name))
 633                         lg4573_spi_startup(CONFIG_LG4573_BUS,
 634                                            CONFIG_LG4573_CS,
 635                                            10000000, SPI_MODE_0);
 636
 637         /* set board_type */
 638         if (gd->board_type == BOARD_TYPE_4)
 639                 env_set("board_type", ARI_BT_4);
 640         else
 641                 env_set("board_type", ARI_BT_7);
 642
 643         return 0;
 644 }
 645
 646 struct i2c_pads_info i2c_pad_info1 = {
 647         .scl = {
 648                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
 649                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 650                 .gp = IMX_GPIO_NR(5, 27)
 651         },
 652         .sda = {
 653                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
 654                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 655                 .gp = IMX_GPIO_NR(5, 26)
 656         }
 657 };
 658
 659 struct i2c_pads_info i2c_pad_info2 = {
 660         .scl = {
 661                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 662                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 663                 .gp = IMX_GPIO_NR(4, 12)
 664         },
 665         .sda = {
 666                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 667                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 668                 .gp = IMX_GPIO_NR(4, 13)
 669         }
 670 };
 671
 672 int dram_init(void)
 673 {
 674         gd->ram_size = imx_ddr_size();
 675
 676         return 0;
 677 }
 678
 679 struct display_info_t const displays[] = {
 680         {
 681                 .bus    = -1,
 682                 .addr   = 0,
 683                 .pixfmt = IPU_PIX_FMT_RGB24,
 684                 .detect = NULL,
 685                 .enable = enable_lvds,
 686                 .mode   = {
 687                         .name           = "lb07wv8",
 688                         .refresh        = 60,
 689                         .xres           = 800,
 690                         .yres           = 480,
 691                         .pixclock       = 30066,
 692                         .left_margin    = 88,
 693                         .right_margin   = 88,
 694                         .upper_margin   = 20,
 695                         .lower_margin   = 20,
 696                         .hsync_len      = 80,
 697                         .vsync_len      = 5,
 698                         .sync           = FB_SYNC_EXT,
 699                         .vmode          = FB_VMODE_NONINTERLACED
 700                 }
 701         }
 702 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
 703         , {
 704                 .bus    = -1,
 705                 .addr   = 0,
 706                 .pixfmt = IPU_PIX_FMT_RGB24,
 707                 .detect = NULL,
 708                 .enable = enable_spi_display,
 709                 .mode   = {
 710                         .name           = "lg4573",
 711                         .refresh        = 57,
 712                         .xres           = 480,
 713                         .yres           = 800,
 714                         .pixclock       = 37037,
 715                         .left_margin    = 59,
 716                         .right_margin   = 10,
 717                         .upper_margin   = 15,
 718                         .lower_margin   = 15,
 719                         .hsync_len      = 10,
 720                         .vsync_len      = 15,
 721                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 722                                           FB_SYNC_VERT_HIGH_ACT,
 723                         .vmode          = FB_VMODE_NONINTERLACED
 724                 }
 725         }
 726 #endif
 727 };
 728 size_t display_count = ARRAY_SIZE(displays);
 729
 730 /* no console on this board */
 731 int board_cfb_skip(void)
 732 {
 733         return 1;
 734 }
 735
 736 iomux_v3_cfg_t nfc_pads[] = {
 737         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 738         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 739         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 740         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 741         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 742         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 743         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 744         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 745         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 746         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 747         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 748         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 749         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 750         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 751         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 752         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 753 };
 754
 755 static void setup_gpmi_nand(void)
 756 {
 757         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 758
 759         /* config gpmi nand iomux */
 760         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 761                                          ARRAY_SIZE(nfc_pads));
 762
 763         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 764         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 765
 766         /* config gpmi and bch clock to 100 MHz */
 767         clrsetbits_le32(&mxc_ccm->cs2cdr,
 768                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 769                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 770                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 771                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 772                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 773                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 774
 775         /* enable ENFC_CLK_ROOT clock */
 776         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 777
 778         /* enable gpmi and bch clock gating */
 779         setbits_le32(&mxc_ccm->CCGR4,
 780                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 781                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 782                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 783                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 784                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 785
 786         /* enable apbh clock gating */
 787         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 788 }
 789
 790 int board_init(void)
 791 {
 792         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 793
 794         /* address of boot parameters */
 795         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 796
 797         setup_spi();
 798
 799         setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 800                   &i2c_pad_info1);
 801         setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 802                   &i2c_pad_info2);
 803         setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 804                   &i2c_pad_info3);
 805         setup_i2c4();
 806
 807         /* SPI NOR Flash read only */
 808         gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
 809         gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
 810         gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
 811
 812         setup_board_gpio();
 813         setup_gpmi_nand();
 814         setup_board_spi();
 815
 816         /* GPIO_1 for USB_OTG_ID */
 817         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 818         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 819         return 0;
 820 }
 821
 822 int checkboard(void)
 823 {
 824         printf("Board: %s\n", CONFIG_BOARDNAME);
 825         return 0;
 826 }
 827
 828 #ifdef CONFIG_USB_EHCI_MX6
 829 int board_ehci_hcd_init(int port)
 830 {
 831         int ret;
 832
 833         ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
 834         if (!ret)
 835                 gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
 836         ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
 837         if (!ret)
 838                 gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
 839         return 0;
 840 }
 841
 842 int board_ehci_power(int port, int on)
 843 {
 844         if (port)
 845                 gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
 846         else
 847                 gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
 848
 849         return 0;
 850 }
 851 #endif
 852
 853 int board_fit_config_name_match(const char *name)
 854 {
 855         if (gd->board_type == BOARD_TYPE_4 &&
 856             strchr(name, 0x34))
 857                 return 0;
 858
 859         if (gd->board_type == BOARD_TYPE_7 &&
 860             strchr(name, 0x37))
 861                 return 0;
 862
 863         return -1;
 864 }
 865
 866 static void do_board_detect(void)
 867 {
 868         int ret;
 869         char s[30];
 870
 871         /* default use board type 7 */
 872         gd->board_type = BOARD_TYPE_7;
 873         if (env_init())
 874                 return;
 875
 876         ret = env_get_f("panel", s, sizeof(s));
 877         if (ret < 0)
 878                 return;
 879
 880         if (!strncmp("lg4573", s, 6))
 881                 gd->board_type = BOARD_TYPE_4;
 882 }
 883
 884 #ifdef CONFIG_DTB_RESELECT
 885 int embedded_dtb_select(void)
 886 {
 887         int rescan;
 888
 889         do_board_detect();
 890         fdtdec_resetup(&rescan);
 891
 892         return 0;
 893 }
 894 #endif