board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <image.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <linux/errno.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/iomux-v3.h>
  20 #include <asm/mach-imx/boot_mode.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <asm/io.h>
  24 #include <asm/arch/sys_proto.h>
  25 #include <bmp_logo.h>
  26 #include <dm/root.h>
  27 #include <env.h>
  28 #include <i2c_eeprom.h>
  29 #include <i2c.h>
  30 #include <micrel.h>
  31 #include <miiphy.h>
  32 #include <lcd.h>
  33 #include <led.h>
  34 #include <power/pmic.h>
  35 #include <power/regulator.h>
  36 #include <power/da9063_pmic.h>
  37 #include <splash.h>
  38 #include <video_fb.h>
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 enum {
  43         BOARD_TYPE_4 = 4,
  44         BOARD_TYPE_7 = 7,
  45 };
  46
  47 #define ARI_BT_4 "aristainetos2_4@2"
  48 #define ARI_BT_7 "aristainetos2_7@1"
  49
  50 int board_phy_config(struct phy_device *phydev)
  51 {
  52         /* control data pad skew - devaddr = 0x02, register = 0x04 */
  53         ksz9031_phy_extended_write(phydev, 0x02,
  54                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  55                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  56         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  57         ksz9031_phy_extended_write(phydev, 0x02,
  58                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  59                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  60         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  61         ksz9031_phy_extended_write(phydev, 0x02,
  62                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  63                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  64         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  65         ksz9031_phy_extended_write(phydev, 0x02,
  66                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  67                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  68
  69         if (phydev->drv->config)
  70                 phydev->drv->config(phydev);
  71
  72         return 0;
  73 }
  74
  75 static int rotate_logo_one(unsigned char *out, unsigned char *in)
  76 {
  77         int   i, j;
  78
  79         for (i = 0; i < BMP_LOGO_WIDTH; i++)
  80                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  81                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  82                         in[i * BMP_LOGO_WIDTH + j];
  83         return 0;
  84 }
  85
  86 /*
  87  * Rotate the BMP_LOGO (only)
  88  * Will only work, if the logo is square, as
  89  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  90  */
  91 void rotate_logo(int rotations)
  92 {
  93         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  94         struct bmp_header *header;
  95         unsigned char *in_logo;
  96         int   i, j;
  97
  98         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
  99                 return;
 100
 101         header = (struct bmp_header *)bmp_logo_bitmap;
 102         in_logo = bmp_logo_bitmap + header->data_offset;
 103
 104         /* one 90 degree rotation */
 105         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 106                 rotate_logo_one(out_logo, in_logo);
 107
 108         /* second 90 degree rotation */
 109         if (rotations == 2  ||  rotations == 3)
 110                 rotate_logo_one(in_logo, out_logo);
 111
 112         /* third 90 degree rotation */
 113         if (rotations == 3)
 114                 rotate_logo_one(out_logo, in_logo);
 115
 116         /* copy result back to original array */
 117         if (rotations == 1  ||  rotations == 3)
 118                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 119                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 120                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 121                                 out_logo[i * BMP_LOGO_WIDTH + j];
 122 }
 123
 124 static void enable_lvds(struct display_info_t const *dev)
 125 {
 126         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 127         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 128         int reg;
 129         s32 timeout = 100000;
 130
 131         /* set PLL5 clock */
 132         reg = readl(&ccm->analog_pll_video);
 133         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 134         writel(reg, &ccm->analog_pll_video);
 135
 136         /* set PLL5 to 232720000Hz */
 137         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 138         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 139         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 140         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 141         writel(reg, &ccm->analog_pll_video);
 142
 143         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 144                &ccm->analog_pll_video_num);
 145         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 146                &ccm->analog_pll_video_denom);
 147
 148         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 149         writel(reg, &ccm->analog_pll_video);
 150
 151         while (timeout--)
 152                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 153                         break;
 154         if (timeout < 0)
 155                 printf("Warning: video pll lock timeout!\n");
 156
 157         reg = readl(&ccm->analog_pll_video);
 158         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 159         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 160         writel(reg, &ccm->analog_pll_video);
 161
 162         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 163         reg = readl(&ccm->cs2cdr);
 164         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 165                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 166         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 167                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 168         writel(reg, &ccm->cs2cdr);
 169
 170         reg = readl(&ccm->cscmr2);
 171         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 172         writel(reg, &ccm->cscmr2);
 173
 174         reg = readl(&ccm->chsccdr);
 175         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 176                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 177         writel(reg, &ccm->chsccdr);
 178
 179         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 180               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 181               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 182               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 183               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 184               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 185               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 186         writel(reg, &iomux->gpr[2]);
 187
 188         reg = readl(&iomux->gpr[3]);
 189         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 190                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 191                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 192         writel(reg, &iomux->gpr[3]);
 193 }
 194
 195 static void enable_spi_display(struct display_info_t const *dev)
 196 {
 197         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 198         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 199         int reg;
 200         s32 timeout = 100000;
 201
 202 #if defined(CONFIG_VIDEO_BMP_LOGO)
 203         rotate_logo(3);  /* portrait display in landscape mode */
 204 #endif
 205
 206         reg = readl(&ccm->cs2cdr);
 207
 208         /* select pll 5 clock */
 209         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 210                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 211         writel(reg, &ccm->cs2cdr);
 212
 213         /* set PLL5 to 197994996Hz */
 214         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 215         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 216         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 217         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 218         writel(reg, &ccm->analog_pll_video);
 219
 220         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 221                &ccm->analog_pll_video_num);
 222         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 223                &ccm->analog_pll_video_denom);
 224
 225         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 226         writel(reg, &ccm->analog_pll_video);
 227
 228         while (timeout--)
 229                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 230                         break;
 231         if (timeout < 0)
 232                 printf("Warning: video pll lock timeout!\n");
 233
 234         reg = readl(&ccm->analog_pll_video);
 235         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 236         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 237         writel(reg, &ccm->analog_pll_video);
 238
 239         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 240         reg = readl(&ccm->cs2cdr);
 241         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 242                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 243         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 244                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 245         writel(reg, &ccm->cs2cdr);
 246
 247         reg = readl(&ccm->cscmr2);
 248         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 249         writel(reg, &ccm->cscmr2);
 250
 251         reg = readl(&ccm->chsccdr);
 252         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 253                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 254         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 255         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 256         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 257         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 258         writel(reg, &ccm->chsccdr);
 259
 260         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 261               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 262               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 263               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 264               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 265               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 266               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 267         writel(reg, &iomux->gpr[2]);
 268
 269         reg = readl(&iomux->gpr[3]);
 270         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 271                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 272                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 273         writel(reg, &iomux->gpr[3]);
 274 }
 275
 276 static void setup_display(void)
 277 {
 278         enable_ipu_clock();
 279 }
 280
 281 static void set_gpr_register(void)
 282 {
 283         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 284
 285         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 286                IOMUXC_GPR1_EXC_MON_SLVE |
 287                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 288                IOMUXC_GPR1_ACT_CS0,
 289                &iomuxc_regs->gpr[1]);
 290         writel(0x0, &iomuxc_regs->gpr[8]);
 291         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 292                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 293                &iomuxc_regs->gpr[12]);
 294 }
 295
 296 extern char __bss_start[], __bss_end[];
 297 int board_early_init_f(void)
 298 {
 299         select_ldb_di_clock_source(MXC_PLL5_CLK);
 300         set_gpr_register();
 301
 302         /*
 303          * clear bss here, so we can use spi driver
 304          * before relocation and read Environment
 305          * from spi flash.
 306          */
 307         memset(__bss_start, 0x00, __bss_end - __bss_start);
 308
 309         return 0;
 310 }
 311
 312 static void setup_one_led(char *label, int state)
 313 {
 314         struct udevice *dev;
 315         int ret;
 316
 317         ret = led_get_by_label(label, &dev);
 318         if (ret == 0)
 319                 led_set_state(dev, state);
 320 }
 321
 322 static void setup_board_gpio(void)
 323 {
 324         setup_one_led("led_ena", LEDST_ON);
 325         /* switch off Status LEDs */
 326         setup_one_led("led_yellow", LEDST_OFF);
 327         setup_one_led("led_red", LEDST_OFF);
 328         setup_one_led("led_green", LEDST_OFF);
 329         setup_one_led("led_blue", LEDST_OFF);
 330 }
 331
 332 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
 333                 " rescueReason=%d "
 334
 335 static void aristainetos_run_rescue_command(int reason)
 336 {
 337         char rescue_reason_command[80];
 338
 339         sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
 340         run_command(rescue_reason_command, 0);
 341 }
 342
 343 static int aristainetos_eeprom(void)
 344 {
 345         struct udevice *dev;
 346         int off;
 347         int ret;
 348         u8 data[0x10];
 349         u8 rescue_reason;
 350
 351         off = fdt_path_offset(gd->fdt_blob, "eeprom0");
 352         if (off < 0) {
 353                 printf("%s: No eeprom0 path offset\n", __func__);
 354                 return off;
 355         }
 356
 357         ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
 358         if (ret) {
 359                 printf("%s: Could not find EEPROM\n", __func__);
 360                 return ret;
 361         }
 362
 363         ret = i2c_set_chip_offset_len(dev, 2);
 364         if (ret)
 365                 return ret;
 366
 367         ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
 368         if (ret) {
 369                 printf("%s: Could not read EEPROM\n", __func__);
 370                 return ret;
 371         }
 372
 373         if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
 374                 rescue_reason = *(uint8_t *)&data[9];
 375                 memset(&data[3], 0xff, 7);
 376                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
 377                 printf("\nBooting into Rescue System (EEPROM)\n");
 378                 aristainetos_run_rescue_command(rescue_reason);
 379                 run_command("run rescue_load_fit rescueboot", 0);
 380         } else if (strncmp((char *)data, "DeF", 3) == 0) {
 381                 memset(data, 0xff, 3);
 382                 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
 383                 printf("\nClear u-boot environment (set back to defaults)\n");
 384                 run_command("run default_env; saveenv; saveenv", 0);
 385         }
 386
 387         return 0;
 388 };
 389
 390 static void aristainetos_bootmode_settings(void)
 391 {
 392         struct gpio_desc *desc;
 393         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 394         unsigned int sbmr1 = readl(&psrc->sbmr1);
 395         char *my_bootdelay;
 396         char bootmode = 0;
 397         int ret;
 398
 399         /*
 400          * Check the boot-source. If booting from NOR Flash,
 401          * disable bootdelay
 402          */
 403         ret = gpio_hog_lookup_name("bootsel0", &desc);
 404         if (!ret)
 405                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 406         ret = gpio_hog_lookup_name("bootsel1", &desc);
 407         if (!ret)
 408                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 409         ret = gpio_hog_lookup_name("bootsel2", &desc);
 410         if (!ret)
 411                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 412
 413         if (bootmode == 7) {
 414                 my_bootdelay = env_get("nor_bootdelay");
 415                 if (my_bootdelay)
 416                         env_set("bootdelay", my_bootdelay);
 417                 else
 418                         env_set("bootdelay", "-2");
 419         }
 420
 421         if (sbmr1 & 0x40) {
 422                 env_set("bootmode", "1");
 423                 printf("SD bootmode jumper set!\n");
 424         } else {
 425                 env_set("bootmode", "0");
 426         }
 427
 428         /* read out some jumper values*/
 429         ret = gpio_hog_lookup_name("env_reset", &desc);
 430         if (!ret) {
 431                 if (dm_gpio_get_value(desc)) {
 432                         printf("\nClear env (set back to defaults)\n");
 433                         run_command("run default_env; saveenv; saveenv", 0);
 434                 }
 435         }
 436         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 437         if (!ret) {
 438                 if (dm_gpio_get_value(desc)) {
 439                         aristainetos_run_rescue_command(16);
 440                         run_command("run rescue_xload_boot", 0);
 441                 }
 442         }
 443 }
 444
 445 #if defined(CONFIG_DM_PMIC_DA9063)
 446 /*
 447  * On the aristainetos2c boards the PMIC needs to be initialized,
 448  * because the Ethernet PHY uses a different regulator that is not
 449  * setup per hardware default. This does not influence the other versions
 450  * as this regulator isn't used there at all.
 451  *
 452  * Unfortunately we have not yet a interface to setup all
 453  * values we need.
 454  */
 455 static int setup_pmic_voltages(void)
 456 {
 457         struct udevice *dev;
 458         int off;
 459         int ret;
 460
 461         off = fdt_path_offset(gd->fdt_blob, "pmic0");
 462         if (off < 0) {
 463                 printf("%s: No pmic path offset\n", __func__);
 464                 return off;
 465         }
 466
 467         ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
 468         if (ret) {
 469                 printf("%s: Could not find PMIC\n", __func__);
 470                 return ret;
 471         }
 472
 473         pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
 474         pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
 475         ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
 476         if (ret < 0) {
 477                 printf("%s: error %d get register\n", __func__, ret);
 478                 return ret;
 479         }
 480         ret &= 0xf0;
 481         ret |= 0x09;
 482         pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
 483         pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
 484         pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
 485
 486         return 0;
 487 }
 488 #else
 489 static int setup_pmic_voltages(void)
 490 {
 491         return 0;
 492 }
 493 #endif
 494
 495 int board_late_init(void)
 496 {
 497         int x, y;
 498
 499         led_default_state();
 500         splash_get_pos(&x, &y);
 501         bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 502
 503         aristainetos_bootmode_settings();
 504
 505         /* eeprom work */
 506         aristainetos_eeprom();
 507
 508         /* set board_type */
 509         if (gd->board_type == BOARD_TYPE_4)
 510                 env_set("board_type", ARI_BT_4);
 511         else
 512                 env_set("board_type", ARI_BT_7);
 513
 514         if (setup_pmic_voltages())
 515                 printf("Error setup PMIC\n");
 516
 517         return 0;
 518 }
 519
 520 int dram_init(void)
 521 {
 522         gd->ram_size = imx_ddr_size();
 523
 524         return 0;
 525 }
 526
 527 struct display_info_t const displays[] = {
 528         {
 529                 .bus    = -1,
 530                 .addr   = 0,
 531                 .pixfmt = IPU_PIX_FMT_RGB24,
 532                 .detect = NULL,
 533                 .enable = enable_lvds,
 534                 .mode   = {
 535                         .name           = "lb07wv8",
 536                         .refresh        = 60,
 537                         .xres           = 800,
 538                         .yres           = 480,
 539                         .pixclock       = 30066,
 540                         .left_margin    = 88,
 541                         .right_margin   = 88,
 542                         .upper_margin   = 20,
 543                         .lower_margin   = 20,
 544                         .hsync_len      = 80,
 545                         .vsync_len      = 5,
 546                         .sync           = FB_SYNC_EXT,
 547                         .vmode          = FB_VMODE_NONINTERLACED
 548                 }
 549         }
 550 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
 551         (CONFIG_SYS_BOARD_VERSION == 3) || \
 552         (CONFIG_SYS_BOARD_VERSION == 4) || \
 553         (CONFIG_SYS_BOARD_VERSION == 5))
 554         , {
 555                 .bus    = -1,
 556                 .addr   = 0,
 557                 .pixfmt = IPU_PIX_FMT_RGB24,
 558                 .detect = NULL,
 559                 .enable = enable_spi_display,
 560                 .mode   = {
 561                         .name           = "lg4573",
 562                         .refresh        = 57,
 563                         .xres           = 480,
 564                         .yres           = 800,
 565                         .pixclock       = 37037,
 566                         .left_margin    = 59,
 567                         .right_margin   = 10,
 568                         .upper_margin   = 15,
 569                         .lower_margin   = 15,
 570                         .hsync_len      = 10,
 571                         .vsync_len      = 15,
 572                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 573                                           FB_SYNC_VERT_HIGH_ACT,
 574                         .vmode          = FB_VMODE_NONINTERLACED
 575                 }
 576         }
 577 #endif
 578 };
 579 size_t display_count = ARRAY_SIZE(displays);
 580
 581 #if defined(CONFIG_MTD_RAW_NAND)
 582 iomux_v3_cfg_t nfc_pads[] = {
 583         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 584         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 585         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 586         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 587         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 588         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 589         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 590         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 591         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 592         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 593         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 594         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 595         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 596         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 597         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 598         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 599 };
 600
 601 static void setup_gpmi_nand(void)
 602 {
 603         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 604
 605         /* config gpmi nand iomux */
 606         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 607                                          ARRAY_SIZE(nfc_pads));
 608
 609         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 610         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 611
 612         /* config gpmi and bch clock to 100 MHz */
 613         clrsetbits_le32(&mxc_ccm->cs2cdr,
 614                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 615                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 616                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 617                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 618                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 619                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 620
 621         /* enable ENFC_CLK_ROOT clock */
 622         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 623
 624         /* enable gpmi and bch clock gating */
 625         setbits_le32(&mxc_ccm->CCGR4,
 626                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 627                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 628                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 629                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 630                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 631
 632         /* enable apbh clock gating */
 633         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 634 }
 635 #else
 636 static void setup_gpmi_nand(void)
 637 {
 638 }
 639 #endif
 640
 641 int board_init(void)
 642 {
 643         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 644
 645         /* address of boot parameters */
 646         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 647
 648         setup_board_gpio();
 649         setup_gpmi_nand();
 650         setup_display();
 651
 652         /* GPIO_1 for USB_OTG_ID */
 653         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 654         return 0;
 655 }
 656
 657 int board_fit_config_name_match(const char *name)
 658 {
 659         if (gd->board_type == BOARD_TYPE_4 &&
 660             strchr(name, 0x34))
 661                 return 0;
 662
 663         if (gd->board_type == BOARD_TYPE_7 &&
 664             strchr(name, 0x37))
 665                 return 0;
 666
 667         return -1;
 668 }
 669
 670 static void do_board_detect(void)
 671 {
 672         int ret;
 673         char s[30];
 674
 675         /* default use board type 7 */
 676         gd->board_type = BOARD_TYPE_7;
 677         if (env_init())
 678                 return;
 679
 680         ret = env_get_f("panel", s, sizeof(s));
 681         if (ret < 0)
 682                 return;
 683
 684         if (!strncmp("lg4573", s, 6))
 685                 gd->board_type = BOARD_TYPE_4;
 686 }
 687
 688 #ifdef CONFIG_DTB_RESELECT
 689 int embedded_dtb_select(void)
 690 {
 691         int rescan;
 692
 693         do_board_detect();
 694         fdtdec_resetup(&rescan);
 695
 696         return 0;
 697 }
 698 #endif