board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <linux/fb.h>
  29 #include <ipu_pixfmt.h>
  30 #include <input.h>
  31 #include <asm/io.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <pwm.h>
  34 #include <env.h>
  35 #include <micrel.h>
  36 #include <spi.h>
  37 #include <video.h>
  38 #include <../drivers/video/imx/ipu.h>
  39 #if defined(CONFIG_VIDEO_BMP_LOGO)
  40         #include <bmp_logo.h>
  41 #endif
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  46         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  50         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  51         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  52
  53 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  54         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  55
  56 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  57                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  58
  59 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  60         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  61         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  62
  63 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  64
  65 #define DISP_PAD_CTRL   (0x10)
  66
  67 #define ECSPI4_CS1              IMX_GPIO_NR(5, 2)
  68
  69 #define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW |                    \
  70         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  71
  72 #if (CONFIG_SYS_BOARD_VERSION == 2)
  73         /* 4.3 display controller */
  74         #define ECSPI1_CS0              IMX_GPIO_NR(4, 9)
  75         #define ECSPI4_CS0              IMX_GPIO_NR(3, 29)
  76 #elif (CONFIG_SYS_BOARD_VERSION == 3)
  77         #define ECSPI1_CS0              IMX_GPIO_NR(2, 30)   /* NOR flash */
  78         /* 4.3 display controller */
  79         #define ECSPI1_CS1              IMX_GPIO_NR(4, 10)
  80 #endif
  81
  82 #define SOFT_RESET_GPIO         IMX_GPIO_NR(7, 13)
  83 #define SD2_DRIVER_ENABLE       IMX_GPIO_NR(7, 8)
  84
  85 struct i2c_pads_info i2c_pad_info3 = {
  86         .scl = {
  87                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  88                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  89                 .gp = IMX_GPIO_NR(1, 5)
  90         },
  91         .sda = {
  92                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  93                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  94                 .gp = IMX_GPIO_NR(1, 6)
  95         }
  96 };
  97
  98 struct i2c_pads_info i2c_pad_info4 = {
  99         .scl = {
 100                 .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
 101                 .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
 102                 .gp = IMX_GPIO_NR(1, 7)
 103         },
 104         .sda = {
 105                 .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
 106                 .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
 107                 .gp = IMX_GPIO_NR(1, 8)
 108         }
 109 };
 110
 111 iomux_v3_cfg_t const uart1_pads[] = {
 112         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 113         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 114         MX6_PAD_EIM_D19__UART1_CTS_B    | MUX_PAD_CTRL(UART_PAD_CTRL),
 115         MX6_PAD_EIM_D20__UART1_RTS_B    | MUX_PAD_CTRL(UART_PAD_CTRL),
 116 };
 117
 118 iomux_v3_cfg_t const uart2_pads[] = {
 119         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 120         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 121 };
 122
 123 iomux_v3_cfg_t const uart3_pads[] = {
 124         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 125         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 126         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 127         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 128 };
 129
 130 iomux_v3_cfg_t const uart4_pads[] = {
 131         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 132         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 133 };
 134
 135 iomux_v3_cfg_t const gpio_pads[] = {
 136         /* LED enable*/
 137         MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
 138         /* LED yellow */
 139         MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 140         /* LED red */
 141 #if (CONFIG_SYS_BOARD_VERSION == 2)
 142         MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 143 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 144         MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 145 #endif
 146         /* LED green */
 147         MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 148         /* LED blue */
 149         MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 150         /* spi flash WP protect */
 151         MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 152         /* spi CS 0 */
 153         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 154         /* spi bus #2 SS driver enable */
 155         MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 156         /* RST_LOC# PHY reset input (has pull-down!)*/
 157         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         /* SD 2 level shifter output enable */
 159         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 160         /* SD1 card detect input */
 161         MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 162         /* SD1 write protect input */
 163         MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 164         /* SD2 card detect input */
 165         MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 166         /* SD2 write protect input */
 167         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 168         /* Touchscreen IRQ */
 169         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 170 };
 171
 172 static iomux_v3_cfg_t const misc_pads[] = {
 173         /* USB_OTG_ID = GPIO1_24*/
 174         MX6_PAD_ENET_RX_ER__USB_OTG_ID          | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         /* H1 Power enable = GPIO1_0*/
 176         MX6_PAD_GPIO_0__USB_H1_PWR              | MUX_PAD_CTRL(NO_PAD_CTRL),
 177         /* OTG Power enable = GPIO4_15*/
 178         MX6_PAD_KEY_ROW4__USB_OTG_PWR           | MUX_PAD_CTRL(NO_PAD_CTRL),
 179 };
 180
 181 iomux_v3_cfg_t const enet_pads[] = {
 182         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 183         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 184         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 185         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 186         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 187         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 188         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 189         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 190         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 191         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 192         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 193         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 194         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 195         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 196         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 197 };
 198
 199 static iomux_v3_cfg_t const backlight_pads[] = {
 200         /* backlight PWM brightness control */
 201         MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 202         /* backlight enable */
 203         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 204         /* LCD power enable */
 205         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 206 };
 207
 208 static iomux_v3_cfg_t const ecspi1_pads[] = {
 209         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 210         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 211         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 212 #if (CONFIG_SYS_BOARD_VERSION == 2)
 213         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 214 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 215         MX6_PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 216         MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 217 #endif
 218 };
 219
 220 static void setup_iomux_enet(void)
 221 {
 222         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 223 }
 224
 225 #if (CONFIG_SYS_BOARD_VERSION == 2)
 226 iomux_v3_cfg_t const ecspi4_pads[] = {
 227         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 228         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
 229         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
 230         MX6_PAD_EIM_A25__GPIO5_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL),
 231         MX6_PAD_EIM_D29__GPIO3_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 232 };
 233 #endif
 234
 235 static iomux_v3_cfg_t const display_pads[] = {
 236         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
 237         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 238         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 239         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 240         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 241         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 242         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 243         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 244         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 245         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 246         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 247         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 248         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 249         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 250         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 251         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 252         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 253         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 254         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 255         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 256         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 257         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 258         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 259         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 260         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 261         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 262         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 263         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 264 };
 265
 266 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 267 {
 268         if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 269 #if (CONFIG_SYS_BOARD_VERSION == 2)
 270                 return IMX_GPIO_NR(5, 2);
 271
 272         if (bus == 0 && cs == 0)
 273                 return IMX_GPIO_NR(4, 9);
 274 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 275                 return ECSPI1_CS0;
 276
 277         if (bus == 0 && cs == 1)
 278                 return ECSPI1_CS1;
 279 #endif
 280         return -1;
 281 }
 282
 283 static void setup_spi(void)
 284 {
 285         int i;
 286
 287         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 288
 289 #if (CONFIG_SYS_BOARD_VERSION == 2)
 290         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
 291 #endif
 292
 293         for (i = 0; i < 4; i++)
 294                 enable_spi_clk(true, i);
 295
 296         gpio_direction_output(ECSPI1_CS0, 1);
 297 #if (CONFIG_SYS_BOARD_VERSION == 2)
 298         gpio_direction_output(ECSPI4_CS1, 0);
 299         /* set cs0 to high (second device on spi bus #4) */
 300         gpio_direction_output(ECSPI4_CS0, 1);
 301 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 302         gpio_direction_output(ECSPI1_CS1, 1);
 303 #endif
 304 }
 305
 306 static void setup_iomux_uart(void)
 307 {
 308         switch (CONFIG_MXC_UART_BASE) {
 309         case UART1_BASE:
 310                 imx_iomux_v3_setup_multiple_pads(uart1_pads,
 311                                                  ARRAY_SIZE(uart1_pads));
 312                 break;
 313         case UART2_BASE:
 314                 imx_iomux_v3_setup_multiple_pads(uart2_pads,
 315                                                  ARRAY_SIZE(uart2_pads));
 316                 break;
 317         case UART3_BASE:
 318                 imx_iomux_v3_setup_multiple_pads(uart3_pads,
 319                                                  ARRAY_SIZE(uart3_pads));
 320                 break;
 321         case UART4_BASE:
 322                 imx_iomux_v3_setup_multiple_pads(uart4_pads,
 323                                                  ARRAY_SIZE(uart4_pads));
 324                 break;
 325         }
 326 }
 327
 328 int board_phy_config(struct phy_device *phydev)
 329 {
 330         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 331         ksz9031_phy_extended_write(phydev, 0x02,
 332                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 333                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 334         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 335         ksz9031_phy_extended_write(phydev, 0x02,
 336                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 337                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 338         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
 339         ksz9031_phy_extended_write(phydev, 0x02,
 340                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 341                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 342         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 343         ksz9031_phy_extended_write(phydev, 0x02,
 344                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 345                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 346
 347         if (phydev->drv->config)
 348                 phydev->drv->config(phydev);
 349
 350         return 0;
 351 }
 352
 353 int board_eth_init(bd_t *bis)
 354 {
 355         setup_iomux_enet();
 356         return cpu_eth_init(bis);
 357 }
 358
 359 static int rotate_logo_one(unsigned char *out, unsigned char *in)
 360 {
 361         int   i, j;
 362
 363         for (i = 0; i < BMP_LOGO_WIDTH; i++)
 364                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 365                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
 366                         in[i * BMP_LOGO_WIDTH + j];
 367         return 0;
 368 }
 369
 370 /*
 371  * Rotate the BMP_LOGO (only)
 372  * Will only work, if the logo is square, as
 373  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
 374  */
 375 void rotate_logo(int rotations)
 376 {
 377         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
 378         unsigned char *in_logo;
 379         int   i, j;
 380
 381         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 382                 return;
 383
 384         in_logo = bmp_logo_bitmap;
 385
 386         /* one 90 degree rotation */
 387         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 388                 rotate_logo_one(out_logo, in_logo);
 389
 390         /* second 90 degree rotation */
 391         if (rotations == 2  ||  rotations == 3)
 392                 rotate_logo_one(in_logo, out_logo);
 393
 394         /* third 90 degree rotation */
 395         if (rotations == 3)
 396                 rotate_logo_one(out_logo, in_logo);
 397
 398         /* copy result back to original array */
 399         if (rotations == 1  ||  rotations == 3)
 400                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 401                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 402                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 403                                 out_logo[i * BMP_LOGO_WIDTH + j];
 404 }
 405
 406 static void enable_display_power(void)
 407 {
 408         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 409                                          ARRAY_SIZE(backlight_pads));
 410
 411         /* backlight enable */
 412         gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
 413         /* LCD power enable */
 414         gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
 415
 416         /* enable backlight PWM 1 */
 417         if (pwm_init(0, 0, 0))
 418                 goto error;
 419         /* duty cycle 500ns, period: 3000ns */
 420         if (pwm_config(0, 50000, 300000))
 421                 goto error;
 422         if (pwm_enable(0))
 423                 goto error;
 424         return;
 425
 426 error:
 427         puts("error init pwm for backlight\n");
 428 }
 429
 430 static void enable_lvds(struct display_info_t const *dev)
 431 {
 432         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 433         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 434         int reg;
 435         s32 timeout = 100000;
 436
 437         /* set PLL5 clock */
 438         reg = readl(&ccm->analog_pll_video);
 439         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 440         writel(reg, &ccm->analog_pll_video);
 441
 442         /* set PLL5 to 232720000Hz */
 443         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 444         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 445         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 446         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 447         writel(reg, &ccm->analog_pll_video);
 448
 449         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 450                &ccm->analog_pll_video_num);
 451         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 452                &ccm->analog_pll_video_denom);
 453
 454         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 455         writel(reg, &ccm->analog_pll_video);
 456
 457         while (timeout--)
 458                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 459                         break;
 460         if (timeout < 0)
 461                 printf("Warning: video pll lock timeout!\n");
 462
 463         reg = readl(&ccm->analog_pll_video);
 464         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 465         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 466         writel(reg, &ccm->analog_pll_video);
 467
 468         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 469         reg = readl(&ccm->cs2cdr);
 470         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 471                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 472         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 473                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 474         writel(reg, &ccm->cs2cdr);
 475
 476         reg = readl(&ccm->cscmr2);
 477         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 478         writel(reg, &ccm->cscmr2);
 479
 480         reg = readl(&ccm->chsccdr);
 481         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 482                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 483         writel(reg, &ccm->chsccdr);
 484
 485         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 486               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 487               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 488               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 489               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 490               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 491               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 492         writel(reg, &iomux->gpr[2]);
 493
 494         reg = readl(&iomux->gpr[3]);
 495         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 496                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 497                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 498         writel(reg, &iomux->gpr[3]);
 499 }
 500
 501 static void enable_spi_display(struct display_info_t const *dev)
 502 {
 503         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 504         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 505         int reg;
 506         s32 timeout = 100000;
 507
 508 #if defined(CONFIG_VIDEO_BMP_LOGO)
 509         rotate_logo(3);  /* portrait display in landscape mode */
 510 #endif
 511
 512         /*
 513          * set ldb clock to 28341000 Hz calculated through the formula:
 514          * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
 515          * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
 516          * see:
 517          * https://community.freescale.com/thread/308170
 518          */
 519         ipu_set_ldb_clock(28341000);
 520
 521         reg = readl(&ccm->cs2cdr);
 522
 523         /* select pll 5 clock */
 524         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 525                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 526         writel(reg, &ccm->cs2cdr);
 527
 528         /* set PLL5 to 197994996Hz */
 529         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 530         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 531         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 532         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 533         writel(reg, &ccm->analog_pll_video);
 534
 535         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 536                &ccm->analog_pll_video_num);
 537         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 538                &ccm->analog_pll_video_denom);
 539
 540         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 541         writel(reg, &ccm->analog_pll_video);
 542
 543         while (timeout--)
 544                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 545                         break;
 546         if (timeout < 0)
 547                 printf("Warning: video pll lock timeout!\n");
 548
 549         reg = readl(&ccm->analog_pll_video);
 550         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 551         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 552         writel(reg, &ccm->analog_pll_video);
 553
 554         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 555         reg = readl(&ccm->cs2cdr);
 556         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 557                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 558         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 559                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 560         writel(reg, &ccm->cs2cdr);
 561
 562         reg = readl(&ccm->cscmr2);
 563         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 564         writel(reg, &ccm->cscmr2);
 565
 566         reg = readl(&ccm->chsccdr);
 567         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 568                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 569         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 570         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 571         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 572         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 573         writel(reg, &ccm->chsccdr);
 574
 575         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 576               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 577               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 578               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 579               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 580               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 581               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 582         writel(reg, &iomux->gpr[2]);
 583
 584         reg = readl(&iomux->gpr[3]);
 585         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 586                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 587                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 588         writel(reg, &iomux->gpr[3]);
 589
 590         imx_iomux_v3_setup_multiple_pads(display_pads,
 591                                          ARRAY_SIZE(display_pads));
 592 }
 593
 594 static void setup_display(void)
 595 {
 596         enable_ipu_clock();
 597         enable_display_power();
 598 }
 599
 600 static void setup_iomux_gpio(void)
 601 {
 602         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 603 }
 604
 605 static void set_gpr_register(void)
 606 {
 607         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 608
 609         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 610                IOMUXC_GPR1_EXC_MON_SLVE |
 611                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 612                IOMUXC_GPR1_ACT_CS0,
 613                &iomuxc_regs->gpr[1]);
 614         writel(0x0, &iomuxc_regs->gpr[8]);
 615         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 616                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 617                &iomuxc_regs->gpr[12]);
 618 }
 619
 620 int board_early_init_f(void)
 621 {
 622         setup_iomux_uart();
 623         setup_iomux_gpio();
 624
 625         gpio_direction_output(SOFT_RESET_GPIO, 1);
 626         gpio_direction_output(SD2_DRIVER_ENABLE, 1);
 627         setup_display();
 628         set_gpr_register();
 629         return 0;
 630 }
 631
 632 static void setup_i2c4(void)
 633 {
 634         setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 635                   &i2c_pad_info4);
 636 }
 637
 638 static void setup_board_gpio(void)
 639 {
 640         /* enable all LEDs */
 641         gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */
 642         gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
 643
 644         /* switch off Status LEDs */
 645 #if (CONFIG_SYS_BOARD_VERSION == 2)
 646         gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
 647         gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
 648         gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
 649         gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
 650         gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
 651         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 652         gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
 653         gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
 654 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 655         gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
 656         gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
 657         gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
 658         gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
 659         gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
 660         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 661         gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
 662         gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
 663 #endif
 664 }
 665
 666 static void setup_board_spi(void)
 667 {
 668         /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
 669         gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
 670 }
 671
 672 int board_late_init(void)
 673 {
 674         char *my_bootdelay;
 675         char bootmode = 0;
 676         char const *panel = env_get("panel");
 677
 678         /*
 679          * Check the boot-source. If booting from NOR Flash,
 680          * disable bootdelay
 681          */
 682         gpio_request(IMX_GPIO_NR(7, 6), "bootsel0");
 683         gpio_direction_input(IMX_GPIO_NR(7, 6));
 684         gpio_request(IMX_GPIO_NR(7, 7), "bootsel1");
 685         gpio_direction_input(IMX_GPIO_NR(7, 7));
 686         gpio_request(IMX_GPIO_NR(7, 1), "bootsel2");
 687         gpio_direction_input(IMX_GPIO_NR(7, 1));
 688         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0;
 689         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1;
 690         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2;
 691
 692         if (bootmode == 7) {
 693                 my_bootdelay = env_get("nor_bootdelay");
 694                 if (my_bootdelay != NULL)
 695                         env_set("bootdelay", my_bootdelay);
 696                 else
 697                         env_set("bootdelay", "-2");
 698         }
 699
 700         /* if we have the lg panel, we can initialze it now */
 701         if (panel)
 702                 if (!strcmp(panel, displays[1].mode.name))
 703                         lg4573_spi_startup(CONFIG_LG4573_BUS,
 704                                            CONFIG_LG4573_CS,
 705                                            10000000, SPI_MODE_0);
 706
 707         return 0;
 708 }
 709
 710 struct i2c_pads_info i2c_pad_info1 = {
 711         .scl = {
 712                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
 713                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 714                 .gp = IMX_GPIO_NR(5, 27)
 715         },
 716         .sda = {
 717                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
 718                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 719                 .gp = IMX_GPIO_NR(5, 26)
 720         }
 721 };
 722
 723 struct i2c_pads_info i2c_pad_info2 = {
 724         .scl = {
 725                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 726                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 727                 .gp = IMX_GPIO_NR(4, 12)
 728         },
 729         .sda = {
 730                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 731                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 732                 .gp = IMX_GPIO_NR(4, 13)
 733         }
 734 };
 735
 736 iomux_v3_cfg_t const usdhc1_pads[] = {
 737         MX6_PAD_SD1_CLK__SD1_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 738         MX6_PAD_SD1_CMD__SD1_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 739         MX6_PAD_SD1_DAT0__SD1_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 740         MX6_PAD_SD1_DAT1__SD1_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 741         MX6_PAD_SD1_DAT2__SD1_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 742         MX6_PAD_SD1_DAT3__SD1_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 743 };
 744
 745 int dram_init(void)
 746 {
 747         gd->ram_size = imx_ddr_size();
 748
 749         return 0;
 750 }
 751
 752 #ifdef CONFIG_FSL_ESDHC_IMX
 753 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 754         {USDHC1_BASE_ADDR},
 755         {USDHC2_BASE_ADDR},
 756 };
 757
 758 int board_mmc_getcd(struct mmc *mmc)
 759 {
 760         return 1;
 761 }
 762
 763 int board_mmc_init(bd_t *bis)
 764 {
 765         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 766         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 767 #if (CONFIG_SYS_BOARD_VERSION == 2)
 768         /*
 769          * usdhc2 has a levelshifter on the carrier board Rev. DV1,
 770          * that will automatically detect the driving direction.
 771          * During initialisation this isn't working correctly,
 772          * which causes DAT3 to be driven low towards the SD-card.
 773          * This causes a SD-card enetring the SPI-Mode
 774          * and therefore getting inaccessible until next power cycle.
 775          * As workaround we drive the DAT3 line as GPIO and set it high.
 776          * This makes usdhc2 unusable in u-boot, but works for the
 777          * initialisation in Linux
 778          */
 779         imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
 780                                MUX_PAD_CTRL(NO_PAD_CTRL));
 781         gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
 782 #endif
 783         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 784 }
 785 #endif
 786
 787 /*
 788  * Do not overwrite the console
 789  * Use always serial for U-Boot console
 790  */
 791 int overwrite_console(void)
 792 {
 793         return 1;
 794 }
 795
 796 struct display_info_t const displays[] = {
 797         {
 798                 .bus    = -1,
 799                 .addr   = 0,
 800                 .pixfmt = IPU_PIX_FMT_RGB24,
 801                 .detect = NULL,
 802                 .enable = enable_lvds,
 803                 .mode   = {
 804                         .name           = "lb07wv8",
 805                         .refresh        = 60,
 806                         .xres           = 800,
 807                         .yres           = 480,
 808                         .pixclock       = 30066,
 809                         .left_margin    = 88,
 810                         .right_margin   = 88,
 811                         .upper_margin   = 20,
 812                         .lower_margin   = 20,
 813                         .hsync_len      = 80,
 814                         .vsync_len      = 5,
 815                         .sync           = FB_SYNC_EXT,
 816                         .vmode          = FB_VMODE_NONINTERLACED
 817                 }
 818         }
 819 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
 820         , {
 821                 .bus    = -1,
 822                 .addr   = 0,
 823                 .pixfmt = IPU_PIX_FMT_RGB24,
 824                 .detect = NULL,
 825                 .enable = enable_spi_display,
 826                 .mode   = {
 827                         .name           = "lg4573",
 828                         .refresh        = 57,
 829                         .xres           = 480,
 830                         .yres           = 800,
 831                         .pixclock       = 37037,
 832                         .left_margin    = 59,
 833                         .right_margin   = 10,
 834                         .upper_margin   = 15,
 835                         .lower_margin   = 15,
 836                         .hsync_len      = 10,
 837                         .vsync_len      = 15,
 838                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 839                                           FB_SYNC_VERT_HIGH_ACT,
 840                         .vmode          = FB_VMODE_NONINTERLACED
 841                 }
 842         }
 843 #endif
 844 };
 845 size_t display_count = ARRAY_SIZE(displays);
 846
 847 /* no console on this board */
 848 int board_cfb_skip(void)
 849 {
 850         return 1;
 851 }
 852
 853 iomux_v3_cfg_t nfc_pads[] = {
 854         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 855         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 856         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 857         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 858         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 859         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 860         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 861         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 862         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 863         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 864         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 865         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 866         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 867         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 868         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 869         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 870 };
 871
 872 static void setup_gpmi_nand(void)
 873 {
 874         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 875
 876         /* config gpmi nand iomux */
 877         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 878                                          ARRAY_SIZE(nfc_pads));
 879
 880         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 881         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 882
 883         /* config gpmi and bch clock to 100 MHz */
 884         clrsetbits_le32(&mxc_ccm->cs2cdr,
 885                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 886                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 887                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 888                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 889                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 890                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 891
 892         /* enable ENFC_CLK_ROOT clock */
 893         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 894
 895         /* enable gpmi and bch clock gating */
 896         setbits_le32(&mxc_ccm->CCGR4,
 897                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 898                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 899                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 900                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 901                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 902
 903         /* enable apbh clock gating */
 904         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 905 }
 906
 907 int board_init(void)
 908 {
 909         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 910
 911         /* address of boot parameters */
 912         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 913
 914         setup_spi();
 915
 916         setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 917                   &i2c_pad_info1);
 918         setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 919                   &i2c_pad_info2);
 920         setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 921                   &i2c_pad_info3);
 922         setup_i2c4();
 923
 924         /* SPI NOR Flash read only */
 925         gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
 926         gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
 927         gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
 928
 929         setup_board_gpio();
 930         setup_gpmi_nand();
 931         setup_board_spi();
 932
 933         /* GPIO_1 for USB_OTG_ID */
 934         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 935         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 936         return 0;
 937 }
 938
 939 int checkboard(void)
 940 {
 941         printf("Board: %s\n", CONFIG_BOARDNAME);
 942         return 0;
 943 }
 944
 945 #ifdef CONFIG_USB_EHCI_MX6
 946 int board_ehci_hcd_init(int port)
 947 {
 948         int ret;
 949
 950         ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
 951         if (!ret)
 952                 gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
 953         ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
 954         if (!ret)
 955                 gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
 956         return 0;
 957 }
 958
 959 int board_ehci_power(int port, int on)
 960 {
 961         if (port)
 962                 gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
 963         else
 964                 gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
 965         return 0;
 966 }
 967 #endif