board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/video.h>
  21 #include <asm/arch/crm_regs.h>
  22 #include <asm/io.h>
  23 #include <asm/arch/sys_proto.h>
  24 #include <bmp_logo.h>
  25 #include <pwm.h>
  26 #include <dm/root.h>
  27 #include <env.h>
  28 #include <micrel.h>
  29 #include <miiphy.h>
  30 #include <lcd.h>
  31 #include <led.h>
  32 #include <splash.h>
  33 #include <video_fb.h>
  34
  35 DECLARE_GLOBAL_DATA_PTR;
  36
  37 enum {
  38         BOARD_TYPE_4 = 4,
  39         BOARD_TYPE_7 = 7,
  40 };
  41
  42 #define ARI_BT_4 "aristainetos2_4@2"
  43 #define ARI_BT_7 "aristainetos2_7@1"
  44
  45 static iomux_v3_cfg_t const backlight_pads[] = {
  46         /* backlight PWM brightness control */
  47         MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  48         /* backlight enable */
  49         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
  50         /* LCD power enable */
  51         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  52 };
  53
  54 int board_phy_config(struct phy_device *phydev)
  55 {
  56         /* control data pad skew - devaddr = 0x02, register = 0x04 */
  57         ksz9031_phy_extended_write(phydev, 0x02,
  58                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  59                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  60         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  61         ksz9031_phy_extended_write(phydev, 0x02,
  62                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  63                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  64         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
  65         ksz9031_phy_extended_write(phydev, 0x02,
  66                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  67                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  68         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  69         ksz9031_phy_extended_write(phydev, 0x02,
  70                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  71                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  72
  73         if (phydev->drv->config)
  74                 phydev->drv->config(phydev);
  75
  76         return 0;
  77 }
  78
  79 static int rotate_logo_one(unsigned char *out, unsigned char *in)
  80 {
  81         int   i, j;
  82
  83         for (i = 0; i < BMP_LOGO_WIDTH; i++)
  84                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
  85                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
  86                         in[i * BMP_LOGO_WIDTH + j];
  87         return 0;
  88 }
  89
  90 /*
  91  * Rotate the BMP_LOGO (only)
  92  * Will only work, if the logo is square, as
  93  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
  94  */
  95 void rotate_logo(int rotations)
  96 {
  97         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
  98         struct bmp_header *header;
  99         unsigned char *in_logo;
 100         int   i, j;
 101
 102         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 103                 return;
 104
 105         header = (struct bmp_header *)bmp_logo_bitmap;
 106         in_logo = bmp_logo_bitmap + header->data_offset;
 107
 108         /* one 90 degree rotation */
 109         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 110                 rotate_logo_one(out_logo, in_logo);
 111
 112         /* second 90 degree rotation */
 113         if (rotations == 2  ||  rotations == 3)
 114                 rotate_logo_one(in_logo, out_logo);
 115
 116         /* third 90 degree rotation */
 117         if (rotations == 3)
 118                 rotate_logo_one(out_logo, in_logo);
 119
 120         /* copy result back to original array */
 121         if (rotations == 1  ||  rotations == 3)
 122                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 123                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 124                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 125                                 out_logo[i * BMP_LOGO_WIDTH + j];
 126 }
 127
 128 static void enable_lvds(struct display_info_t const *dev)
 129 {
 130         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 131         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 132         int reg;
 133         s32 timeout = 100000;
 134
 135         /* set PLL5 clock */
 136         reg = readl(&ccm->analog_pll_video);
 137         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 138         writel(reg, &ccm->analog_pll_video);
 139
 140         /* set PLL5 to 232720000Hz */
 141         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 142         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 143         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 144         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 145         writel(reg, &ccm->analog_pll_video);
 146
 147         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 148                &ccm->analog_pll_video_num);
 149         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 150                &ccm->analog_pll_video_denom);
 151
 152         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 153         writel(reg, &ccm->analog_pll_video);
 154
 155         while (timeout--)
 156                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 157                         break;
 158         if (timeout < 0)
 159                 printf("Warning: video pll lock timeout!\n");
 160
 161         reg = readl(&ccm->analog_pll_video);
 162         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 163         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 164         writel(reg, &ccm->analog_pll_video);
 165
 166         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 167         reg = readl(&ccm->cs2cdr);
 168         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 169                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 170         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 171                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 172         writel(reg, &ccm->cs2cdr);
 173
 174         reg = readl(&ccm->cscmr2);
 175         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 176         writel(reg, &ccm->cscmr2);
 177
 178         reg = readl(&ccm->chsccdr);
 179         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 180                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 181         writel(reg, &ccm->chsccdr);
 182
 183         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 184               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 185               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 186               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 187               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 188               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 189               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 190         writel(reg, &iomux->gpr[2]);
 191
 192         reg = readl(&iomux->gpr[3]);
 193         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 194                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 195                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 196         writel(reg, &iomux->gpr[3]);
 197 }
 198
 199 static void enable_spi_display(struct display_info_t const *dev)
 200 {
 201         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 202         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 203         int reg;
 204         s32 timeout = 100000;
 205
 206 #if defined(CONFIG_VIDEO_BMP_LOGO)
 207         rotate_logo(3);  /* portrait display in landscape mode */
 208 #endif
 209
 210         reg = readl(&ccm->cs2cdr);
 211
 212         /* select pll 5 clock */
 213         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 214                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 215         writel(reg, &ccm->cs2cdr);
 216
 217         /* set PLL5 to 197994996Hz */
 218         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 219         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 220         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 221         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 222         writel(reg, &ccm->analog_pll_video);
 223
 224         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 225                &ccm->analog_pll_video_num);
 226         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 227                &ccm->analog_pll_video_denom);
 228
 229         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 230         writel(reg, &ccm->analog_pll_video);
 231
 232         while (timeout--)
 233                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 234                         break;
 235         if (timeout < 0)
 236                 printf("Warning: video pll lock timeout!\n");
 237
 238         reg = readl(&ccm->analog_pll_video);
 239         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 240         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 241         writel(reg, &ccm->analog_pll_video);
 242
 243         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 244         reg = readl(&ccm->cs2cdr);
 245         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 246                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 247         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 248                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 249         writel(reg, &ccm->cs2cdr);
 250
 251         reg = readl(&ccm->cscmr2);
 252         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 253         writel(reg, &ccm->cscmr2);
 254
 255         reg = readl(&ccm->chsccdr);
 256         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 257                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 258         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 259         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 260         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 261         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 262         writel(reg, &ccm->chsccdr);
 263
 264         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 265               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 266               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 267               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 268               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 269               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 270               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 271         writel(reg, &iomux->gpr[2]);
 272
 273         reg = readl(&iomux->gpr[3]);
 274         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 275                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 276                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 277         writel(reg, &iomux->gpr[3]);
 278 }
 279
 280 static void setup_display(void)
 281 {
 282         enable_ipu_clock();
 283 }
 284
 285 static void set_gpr_register(void)
 286 {
 287         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 288
 289         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 290                IOMUXC_GPR1_EXC_MON_SLVE |
 291                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 292                IOMUXC_GPR1_ACT_CS0,
 293                &iomuxc_regs->gpr[1]);
 294         writel(0x0, &iomuxc_regs->gpr[8]);
 295         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 296                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 297                &iomuxc_regs->gpr[12]);
 298 }
 299
 300 extern char __bss_start[], __bss_end[];
 301 int board_early_init_f(void)
 302 {
 303         select_ldb_di_clock_source(MXC_PLL5_CLK);
 304         set_gpr_register();
 305
 306         /*
 307          * clear bss here, so we can use spi driver
 308          * before relocation and read Environment
 309          * from spi flash.
 310          */
 311         memset(__bss_start, 0x00, __bss_end - __bss_start);
 312
 313         return 0;
 314 }
 315
 316 static void setup_one_led(char *label, int state)
 317 {
 318         struct udevice *dev;
 319         int ret;
 320
 321         ret = led_get_by_label(label, &dev);
 322         if (ret == 0)
 323                 led_set_state(dev, state);
 324 }
 325
 326 static void setup_board_gpio(void)
 327 {
 328         setup_one_led("led_ena", LEDST_ON);
 329         /* switch off Status LEDs */
 330         setup_one_led("led_yellow", LEDST_OFF);
 331         setup_one_led("led_red", LEDST_OFF);
 332         setup_one_led("led_green", LEDST_OFF);
 333         setup_one_led("led_blue", LEDST_OFF);
 334 }
 335
 336 int board_late_init(void)
 337 {
 338         char *my_bootdelay;
 339         char bootmode = 0;
 340         struct gpio_desc *desc;
 341         int x, y;
 342         int ret;
 343
 344         led_default_state();
 345         splash_get_pos(&x, &y);
 346         bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
 347         /*
 348          * Check the boot-source. If booting from NOR Flash,
 349          * disable bootdelay
 350          */
 351         desc = gpio_hog_lookup_name("bootsel0");
 352         if (desc)
 353                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
 354         desc = gpio_hog_lookup_name("bootsel1");
 355         if (desc)
 356                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
 357         desc = gpio_hog_lookup_name("bootsel2");
 358         if (desc)
 359                 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
 360
 361         if (bootmode == 7) {
 362                 my_bootdelay = env_get("nor_bootdelay");
 363                 if (my_bootdelay != NULL)
 364                         env_set("bootdelay", my_bootdelay);
 365                 else
 366                         env_set("bootdelay", "-2");
 367         }
 368
 369         /* read out some jumper values*/
 370         ret = gpio_hog_lookup_name("env_reset", &desc);
 371         if (!ret) {
 372                 if (dm_gpio_get_value(desc)) {
 373                         printf("\nClear env (set back to defaults)\n");
 374                         run_command("run default_env; saveenv; saveenv", 0);
 375                 }
 376         }
 377         ret = gpio_hog_lookup_name("boot_rescue", &desc);
 378         if (!ret) {
 379                 if (dm_gpio_get_value(desc)) {
 380                         aristainetos_run_rescue_command(16);
 381                         run_command("run rescue_xload_boot", 0);
 382                 }
 383         }
 384
 385         /* set board_type */
 386         if (gd->board_type == BOARD_TYPE_4)
 387                 env_set("board_type", ARI_BT_4);
 388         else
 389                 env_set("board_type", ARI_BT_7);
 390
 391         return 0;
 392 }
 393
 394 int dram_init(void)
 395 {
 396         gd->ram_size = imx_ddr_size();
 397
 398         return 0;
 399 }
 400
 401 struct display_info_t const displays[] = {
 402         {
 403                 .bus    = -1,
 404                 .addr   = 0,
 405                 .pixfmt = IPU_PIX_FMT_RGB24,
 406                 .detect = NULL,
 407                 .enable = enable_lvds,
 408                 .mode   = {
 409                         .name           = "lb07wv8",
 410                         .refresh        = 60,
 411                         .xres           = 800,
 412                         .yres           = 480,
 413                         .pixclock       = 30066,
 414                         .left_margin    = 88,
 415                         .right_margin   = 88,
 416                         .upper_margin   = 20,
 417                         .lower_margin   = 20,
 418                         .hsync_len      = 80,
 419                         .vsync_len      = 5,
 420                         .sync           = FB_SYNC_EXT,
 421                         .vmode          = FB_VMODE_NONINTERLACED
 422                 }
 423         }
 424 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
 425         , {
 426                 .bus    = -1,
 427                 .addr   = 0,
 428                 .pixfmt = IPU_PIX_FMT_RGB24,
 429                 .detect = NULL,
 430                 .enable = enable_spi_display,
 431                 .mode   = {
 432                         .name           = "lg4573",
 433                         .refresh        = 57,
 434                         .xres           = 480,
 435                         .yres           = 800,
 436                         .pixclock       = 37037,
 437                         .left_margin    = 59,
 438                         .right_margin   = 10,
 439                         .upper_margin   = 15,
 440                         .lower_margin   = 15,
 441                         .hsync_len      = 10,
 442                         .vsync_len      = 15,
 443                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 444                                           FB_SYNC_VERT_HIGH_ACT,
 445                         .vmode          = FB_VMODE_NONINTERLACED
 446                 }
 447         }
 448 #endif
 449 };
 450 size_t display_count = ARRAY_SIZE(displays);
 451
 452 iomux_v3_cfg_t nfc_pads[] = {
 453         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 454         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 455         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 456         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 457         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 458         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 459         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 460         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 461         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 462         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 463         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 464         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 465         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 466         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 467         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 468         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 469 };
 470
 471 static void setup_gpmi_nand(void)
 472 {
 473         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 474
 475         /* config gpmi nand iomux */
 476         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 477                                          ARRAY_SIZE(nfc_pads));
 478
 479         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 480         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 481
 482         /* config gpmi and bch clock to 100 MHz */
 483         clrsetbits_le32(&mxc_ccm->cs2cdr,
 484                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 485                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 486                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 487                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 488                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 489                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 490
 491         /* enable ENFC_CLK_ROOT clock */
 492         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 493
 494         /* enable gpmi and bch clock gating */
 495         setbits_le32(&mxc_ccm->CCGR4,
 496                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 497                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 498                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 499                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 500                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 501
 502         /* enable apbh clock gating */
 503         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 504 }
 505
 506 int board_init(void)
 507 {
 508         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 509
 510         /* address of boot parameters */
 511         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 512
 513         setup_board_gpio();
 514         setup_gpmi_nand();
 515         setup_display();
 516
 517         /* GPIO_1 for USB_OTG_ID */
 518         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 519         return 0;
 520 }
 521
 522 int checkboard(void)
 523 {
 524         printf("Board: %s\n", CONFIG_BOARDNAME);
 525         return 0;
 526 }
 527
 528 int board_fit_config_name_match(const char *name)
 529 {
 530         if (gd->board_type == BOARD_TYPE_4 &&
 531             strchr(name, 0x34))
 532                 return 0;
 533
 534         if (gd->board_type == BOARD_TYPE_7 &&
 535             strchr(name, 0x37))
 536                 return 0;
 537
 538         return -1;
 539 }
 540
 541 static void do_board_detect(void)
 542 {
 543         int ret;
 544         char s[30];
 545
 546         /* default use board type 7 */
 547         gd->board_type = BOARD_TYPE_7;
 548         if (env_init())
 549                 return;
 550
 551         ret = env_get_f("panel", s, sizeof(s));
 552         if (ret < 0)
 553                 return;
 554
 555         if (!strncmp("lg4573", s, 6))
 556                 gd->board_type = BOARD_TYPE_4;
 557 }
 558
 559 #ifdef CONFIG_DTB_RESELECT
 560 int embedded_dtb_select(void)
 561 {
 562         int rescan;
 563
 564         do_board_detect();
 565         fdtdec_resetup(&rescan);
 566
 567         return 0;
 568 }
 569 #endif