board/aristainetos/aristainetos.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/imx-regs.h>
  14 #include <asm/arch/iomux.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <linux/errno.h>
  17 #include <asm/gpio.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/boot_mode.h>
  20 #include <asm/mach-imx/mxc_i2c.h>
  21 #include <asm/mach-imx/video.h>
  22 #include <mmc.h>
  23 #include <fsl_esdhc_imx.h>
  24 #include <miiphy.h>
  25 #include <netdev.h>
  26 #include <asm/arch/mxc_hdmi.h>
  27 #include <asm/arch/crm_regs.h>
  28 #include <linux/fb.h>
  29 #include <ipu_pixfmt.h>
  30 #include <input.h>
  31 #include <asm/io.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <pwm.h>
  34 #include <dm/root.h>
  35 #include <env.h>
  36 #include <micrel.h>
  37 #include <spi.h>
  38 #include <video.h>
  39 #include <../drivers/video/imx/ipu.h>
  40 #if defined(CONFIG_VIDEO_BMP_LOGO)
  41         #include <bmp_logo.h>
  42 #endif
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  47         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  48         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  49
  50 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  51         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  52
  53 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  54                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  55
  56 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP |                  \
  57         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  58         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  59
  60 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  61
  62 #define DISP_PAD_CTRL   (0x10)
  63
  64 #define ECSPI4_CS1              IMX_GPIO_NR(5, 2)
  65
  66 #define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW |                    \
  67         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  68
  69 #if (CONFIG_SYS_BOARD_VERSION == 2)
  70         /* 4.3 display controller */
  71         #define ECSPI1_CS0              IMX_GPIO_NR(4, 9)
  72         #define ECSPI4_CS0              IMX_GPIO_NR(3, 29)
  73 #elif (CONFIG_SYS_BOARD_VERSION == 3)
  74         #define ECSPI1_CS0              IMX_GPIO_NR(2, 30)   /* NOR flash */
  75         /* 4.3 display controller */
  76         #define ECSPI1_CS1              IMX_GPIO_NR(4, 10)
  77 #endif
  78
  79 #define SOFT_RESET_GPIO         IMX_GPIO_NR(7, 13)
  80 #define SD2_DRIVER_ENABLE       IMX_GPIO_NR(7, 8)
  81
  82 enum {
  83         BOARD_TYPE_4 = 4,
  84         BOARD_TYPE_7 = 7,
  85 };
  86
  87 #define ARI_BT_4 "aristainetos2_4@2"
  88 #define ARI_BT_7 "aristainetos2_7@1"
  89
  90 struct i2c_pads_info i2c_pad_info3 = {
  91         .scl = {
  92                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  93                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  94                 .gp = IMX_GPIO_NR(1, 5)
  95         },
  96         .sda = {
  97                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  98                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  99                 .gp = IMX_GPIO_NR(1, 6)
 100         }
 101 };
 102
 103 struct i2c_pads_info i2c_pad_info4 = {
 104         .scl = {
 105                 .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
 106                 .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
 107                 .gp = IMX_GPIO_NR(1, 7)
 108         },
 109         .sda = {
 110                 .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
 111                 .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
 112                 .gp = IMX_GPIO_NR(1, 8)
 113         }
 114 };
 115
 116 iomux_v3_cfg_t const gpio_pads[] = {
 117         /* LED enable*/
 118         MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
 119         /* LED yellow */
 120         MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 121         /* LED red */
 122 #if (CONFIG_SYS_BOARD_VERSION == 2)
 123         MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 124 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 125         MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 126 #endif
 127         /* LED green */
 128         MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 129         /* LED blue */
 130         MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 131         /* spi flash WP protect */
 132         MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 133         /* spi CS 0 */
 134         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 135         /* spi bus #2 SS driver enable */
 136         MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 137         /* RST_LOC# PHY reset input (has pull-down!)*/
 138         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 139         /* SD 2 level shifter output enable */
 140         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 141         /* SD1 card detect input */
 142         MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 143         /* SD1 write protect input */
 144         MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 145         /* SD2 card detect input */
 146         MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 147         /* SD2 write protect input */
 148         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 149         /* Touchscreen IRQ */
 150         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 151 };
 152
 153 static iomux_v3_cfg_t const misc_pads[] = {
 154         /* USB_OTG_ID = GPIO1_24*/
 155         MX6_PAD_ENET_RX_ER__USB_OTG_ID          | MUX_PAD_CTRL(NO_PAD_CTRL),
 156         /* H1 Power enable = GPIO1_0*/
 157         MX6_PAD_GPIO_0__USB_H1_PWR              | MUX_PAD_CTRL(NO_PAD_CTRL),
 158         /* OTG Power enable = GPIO4_15*/
 159         MX6_PAD_KEY_ROW4__USB_OTG_PWR           | MUX_PAD_CTRL(NO_PAD_CTRL),
 160 };
 161
 162 iomux_v3_cfg_t const enet_pads[] = {
 163         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 172         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 173         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 174         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 175         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 176         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 177         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 178 };
 179
 180 static iomux_v3_cfg_t const backlight_pads[] = {
 181         /* backlight PWM brightness control */
 182         MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 183         /* backlight enable */
 184         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 185         /* LCD power enable */
 186         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 187 };
 188
 189 static iomux_v3_cfg_t const ecspi1_pads[] = {
 190         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 191         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 192         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 193 #if (CONFIG_SYS_BOARD_VERSION == 2)
 194         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 195 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 196         MX6_PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 197         MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 198 #endif
 199 };
 200
 201 static void setup_iomux_enet(void)
 202 {
 203         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 204 }
 205
 206 #if (CONFIG_SYS_BOARD_VERSION == 2)
 207 iomux_v3_cfg_t const ecspi4_pads[] = {
 208         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 209         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
 210         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
 211         MX6_PAD_EIM_A25__GPIO5_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL),
 212         MX6_PAD_EIM_D29__GPIO3_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 213 };
 214 #endif
 215
 216 static iomux_v3_cfg_t const display_pads[] = {
 217         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
 218         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 219         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 220         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 221         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 222         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 223         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 224         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 225         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 226         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 227         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 228         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 229         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 230         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 231         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 232         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 233         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 234         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 235         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 236         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 237         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 238         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 239         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 240         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 241         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 242         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 243         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 244         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 245 };
 246
 247 int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
 248 {
 249         if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 250 #if (CONFIG_SYS_BOARD_VERSION == 2)
 251                 return IMX_GPIO_NR(5, 2);
 252
 253         if (bus == 0 && cs == 0)
 254                 return IMX_GPIO_NR(4, 9);
 255 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 256                 return ECSPI1_CS0;
 257
 258         if (bus == 0 && cs == 1)
 259                 return ECSPI1_CS1;
 260 #endif
 261         return -1;
 262 }
 263
 264 static void setup_spi(void)
 265 {
 266         int i;
 267
 268         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 269
 270 #if (CONFIG_SYS_BOARD_VERSION == 2)
 271         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
 272 #endif
 273
 274         for (i = 0; i < 4; i++)
 275                 enable_spi_clk(true, i);
 276
 277         gpio_direction_output(ECSPI1_CS0, 1);
 278 #if (CONFIG_SYS_BOARD_VERSION == 2)
 279         gpio_direction_output(ECSPI4_CS1, 0);
 280         /* set cs0 to high (second device on spi bus #4) */
 281         gpio_direction_output(ECSPI4_CS0, 1);
 282 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 283         gpio_direction_output(ECSPI1_CS1, 1);
 284 #endif
 285 }
 286
 287 int board_phy_config(struct phy_device *phydev)
 288 {
 289         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 290         ksz9031_phy_extended_write(phydev, 0x02,
 291                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 292                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 293         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 294         ksz9031_phy_extended_write(phydev, 0x02,
 295                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 296                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 297         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
 298         ksz9031_phy_extended_write(phydev, 0x02,
 299                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 300                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 301         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 302         ksz9031_phy_extended_write(phydev, 0x02,
 303                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 304                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 305
 306         if (phydev->drv->config)
 307                 phydev->drv->config(phydev);
 308
 309         return 0;
 310 }
 311
 312 int board_eth_init(bd_t *bis)
 313 {
 314         setup_iomux_enet();
 315         return cpu_eth_init(bis);
 316 }
 317
 318 static int rotate_logo_one(unsigned char *out, unsigned char *in)
 319 {
 320         int   i, j;
 321
 322         for (i = 0; i < BMP_LOGO_WIDTH; i++)
 323                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 324                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
 325                         in[i * BMP_LOGO_WIDTH + j];
 326         return 0;
 327 }
 328
 329 /*
 330  * Rotate the BMP_LOGO (only)
 331  * Will only work, if the logo is square, as
 332  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
 333  */
 334 void rotate_logo(int rotations)
 335 {
 336         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
 337         unsigned char *in_logo;
 338         int   i, j;
 339
 340         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 341                 return;
 342
 343         in_logo = bmp_logo_bitmap;
 344
 345         /* one 90 degree rotation */
 346         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 347                 rotate_logo_one(out_logo, in_logo);
 348
 349         /* second 90 degree rotation */
 350         if (rotations == 2  ||  rotations == 3)
 351                 rotate_logo_one(in_logo, out_logo);
 352
 353         /* third 90 degree rotation */
 354         if (rotations == 3)
 355                 rotate_logo_one(out_logo, in_logo);
 356
 357         /* copy result back to original array */
 358         if (rotations == 1  ||  rotations == 3)
 359                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 360                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 361                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 362                                 out_logo[i * BMP_LOGO_WIDTH + j];
 363 }
 364
 365 static void enable_display_power(void)
 366 {
 367         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 368                                          ARRAY_SIZE(backlight_pads));
 369
 370         /* backlight enable */
 371         gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
 372         /* LCD power enable */
 373         gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
 374
 375         /* enable backlight PWM 1 */
 376         if (pwm_init(0, 0, 0))
 377                 goto error;
 378         /* duty cycle 500ns, period: 3000ns */
 379         if (pwm_config(0, 50000, 300000))
 380                 goto error;
 381         if (pwm_enable(0))
 382                 goto error;
 383         return;
 384
 385 error:
 386         puts("error init pwm for backlight\n");
 387 }
 388
 389 static void enable_lvds(struct display_info_t const *dev)
 390 {
 391         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 392         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 393         int reg;
 394         s32 timeout = 100000;
 395
 396         /* set PLL5 clock */
 397         reg = readl(&ccm->analog_pll_video);
 398         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 399         writel(reg, &ccm->analog_pll_video);
 400
 401         /* set PLL5 to 232720000Hz */
 402         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 403         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 404         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 405         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 406         writel(reg, &ccm->analog_pll_video);
 407
 408         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 409                &ccm->analog_pll_video_num);
 410         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 411                &ccm->analog_pll_video_denom);
 412
 413         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 414         writel(reg, &ccm->analog_pll_video);
 415
 416         while (timeout--)
 417                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 418                         break;
 419         if (timeout < 0)
 420                 printf("Warning: video pll lock timeout!\n");
 421
 422         reg = readl(&ccm->analog_pll_video);
 423         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 424         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 425         writel(reg, &ccm->analog_pll_video);
 426
 427         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 428         reg = readl(&ccm->cs2cdr);
 429         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 430                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 431         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 432                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 433         writel(reg, &ccm->cs2cdr);
 434
 435         reg = readl(&ccm->cscmr2);
 436         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 437         writel(reg, &ccm->cscmr2);
 438
 439         reg = readl(&ccm->chsccdr);
 440         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 441                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 442         writel(reg, &ccm->chsccdr);
 443
 444         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 445               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 446               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 447               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 448               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 449               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 450               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 451         writel(reg, &iomux->gpr[2]);
 452
 453         reg = readl(&iomux->gpr[3]);
 454         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 455                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 456                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 457         writel(reg, &iomux->gpr[3]);
 458 }
 459
 460 static void enable_spi_display(struct display_info_t const *dev)
 461 {
 462         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 463         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 464         int reg;
 465         s32 timeout = 100000;
 466
 467 #if defined(CONFIG_VIDEO_BMP_LOGO)
 468         rotate_logo(3);  /* portrait display in landscape mode */
 469 #endif
 470
 471         /*
 472          * set ldb clock to 28341000 Hz calculated through the formula:
 473          * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
 474          * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
 475          * see:
 476          * https://community.freescale.com/thread/308170
 477          */
 478         ipu_set_ldb_clock(28341000);
 479
 480         reg = readl(&ccm->cs2cdr);
 481
 482         /* select pll 5 clock */
 483         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 484                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 485         writel(reg, &ccm->cs2cdr);
 486
 487         /* set PLL5 to 197994996Hz */
 488         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 489         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 490         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 491         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 492         writel(reg, &ccm->analog_pll_video);
 493
 494         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 495                &ccm->analog_pll_video_num);
 496         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 497                &ccm->analog_pll_video_denom);
 498
 499         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 500         writel(reg, &ccm->analog_pll_video);
 501
 502         while (timeout--)
 503                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 504                         break;
 505         if (timeout < 0)
 506                 printf("Warning: video pll lock timeout!\n");
 507
 508         reg = readl(&ccm->analog_pll_video);
 509         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 510         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 511         writel(reg, &ccm->analog_pll_video);
 512
 513         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 514         reg = readl(&ccm->cs2cdr);
 515         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 516                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 517         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 518                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 519         writel(reg, &ccm->cs2cdr);
 520
 521         reg = readl(&ccm->cscmr2);
 522         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 523         writel(reg, &ccm->cscmr2);
 524
 525         reg = readl(&ccm->chsccdr);
 526         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 527                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 528         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 529         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 530         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 531         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 532         writel(reg, &ccm->chsccdr);
 533
 534         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 535               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 536               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 537               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 538               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 539               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 540               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 541         writel(reg, &iomux->gpr[2]);
 542
 543         reg = readl(&iomux->gpr[3]);
 544         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 545                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 546                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 547         writel(reg, &iomux->gpr[3]);
 548
 549         imx_iomux_v3_setup_multiple_pads(display_pads,
 550                                          ARRAY_SIZE(display_pads));
 551 }
 552
 553 static void setup_display(void)
 554 {
 555         enable_ipu_clock();
 556         enable_display_power();
 557 }
 558
 559 static void setup_iomux_gpio(void)
 560 {
 561         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 562 }
 563
 564 static void set_gpr_register(void)
 565 {
 566         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 567
 568         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 569                IOMUXC_GPR1_EXC_MON_SLVE |
 570                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 571                IOMUXC_GPR1_ACT_CS0,
 572                &iomuxc_regs->gpr[1]);
 573         writel(0x0, &iomuxc_regs->gpr[8]);
 574         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 575                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 576                &iomuxc_regs->gpr[12]);
 577 }
 578
 579 extern char __bss_start[], __bss_end[];
 580 int board_early_init_f(void)
 581 {
 582         setup_iomux_gpio();
 583
 584         gpio_direction_output(SOFT_RESET_GPIO, 1);
 585         gpio_direction_output(SD2_DRIVER_ENABLE, 1);
 586         setup_display();
 587         set_gpr_register();
 588
 589         /*
 590          * clear bss here, so we can use spi driver
 591          * before relocation and read Environment
 592          * from spi flash.
 593          */
 594         memset(__bss_start, 0x00, __bss_end - __bss_start);
 595
 596         return 0;
 597 }
 598
 599 static void setup_i2c4(void)
 600 {
 601         setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 602                   &i2c_pad_info4);
 603 }
 604
 605 static void setup_board_gpio(void)
 606 {
 607         /* enable all LEDs */
 608         gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */
 609         gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
 610
 611         /* switch off Status LEDs */
 612 #if (CONFIG_SYS_BOARD_VERSION == 2)
 613         gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
 614         gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
 615         gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
 616         gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
 617         gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
 618         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 619         gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
 620         gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
 621 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 622         gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
 623         gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
 624         gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
 625         gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
 626         gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
 627         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 628         gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
 629         gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
 630 #endif
 631 }
 632
 633 static void setup_board_spi(void)
 634 {
 635         /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
 636         gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
 637 }
 638
 639 int board_late_init(void)
 640 {
 641         char *my_bootdelay;
 642         char bootmode = 0;
 643         char const *panel = env_get("panel");
 644
 645         /*
 646          * Check the boot-source. If booting from NOR Flash,
 647          * disable bootdelay
 648          */
 649         gpio_request(IMX_GPIO_NR(7, 6), "bootsel0");
 650         gpio_direction_input(IMX_GPIO_NR(7, 6));
 651         gpio_request(IMX_GPIO_NR(7, 7), "bootsel1");
 652         gpio_direction_input(IMX_GPIO_NR(7, 7));
 653         gpio_request(IMX_GPIO_NR(7, 1), "bootsel2");
 654         gpio_direction_input(IMX_GPIO_NR(7, 1));
 655         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0;
 656         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1;
 657         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2;
 658
 659         if (bootmode == 7) {
 660                 my_bootdelay = env_get("nor_bootdelay");
 661                 if (my_bootdelay != NULL)
 662                         env_set("bootdelay", my_bootdelay);
 663                 else
 664                         env_set("bootdelay", "-2");
 665         }
 666
 667         /* if we have the lg panel, we can initialze it now */
 668         if (panel)
 669                 if (!strcmp(panel, displays[1].mode.name))
 670                         lg4573_spi_startup(CONFIG_LG4573_BUS,
 671                                            CONFIG_LG4573_CS,
 672                                            10000000, SPI_MODE_0);
 673
 674         /* set board_type */
 675         if (gd->board_type == BOARD_TYPE_4)
 676                 env_set("board_type", ARI_BT_4);
 677         else
 678                 env_set("board_type", ARI_BT_7);
 679
 680         return 0;
 681 }
 682
 683 struct i2c_pads_info i2c_pad_info1 = {
 684         .scl = {
 685                 .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
 686                 .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
 687                 .gp = IMX_GPIO_NR(5, 27)
 688         },
 689         .sda = {
 690                 .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
 691                 .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
 692                 .gp = IMX_GPIO_NR(5, 26)
 693         }
 694 };
 695
 696 struct i2c_pads_info i2c_pad_info2 = {
 697         .scl = {
 698                 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 699                 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 700                 .gp = IMX_GPIO_NR(4, 12)
 701         },
 702         .sda = {
 703                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 704                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 705                 .gp = IMX_GPIO_NR(4, 13)
 706         }
 707 };
 708
 709 iomux_v3_cfg_t const usdhc1_pads[] = {
 710         MX6_PAD_SD1_CLK__SD1_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 711         MX6_PAD_SD1_CMD__SD1_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 712         MX6_PAD_SD1_DAT0__SD1_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 713         MX6_PAD_SD1_DAT1__SD1_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 714         MX6_PAD_SD1_DAT2__SD1_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 715         MX6_PAD_SD1_DAT3__SD1_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 716 };
 717
 718 int dram_init(void)
 719 {
 720         gd->ram_size = imx_ddr_size();
 721
 722         return 0;
 723 }
 724
 725 #ifdef CONFIG_FSL_ESDHC_IMX
 726 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 727         {USDHC1_BASE_ADDR},
 728         {USDHC2_BASE_ADDR},
 729 };
 730
 731 int board_mmc_getcd(struct mmc *mmc)
 732 {
 733         return 1;
 734 }
 735
 736 int board_mmc_init(bd_t *bis)
 737 {
 738         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 739         imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
 740 #if (CONFIG_SYS_BOARD_VERSION == 2)
 741         /*
 742          * usdhc2 has a levelshifter on the carrier board Rev. DV1,
 743          * that will automatically detect the driving direction.
 744          * During initialisation this isn't working correctly,
 745          * which causes DAT3 to be driven low towards the SD-card.
 746          * This causes a SD-card enetring the SPI-Mode
 747          * and therefore getting inaccessible until next power cycle.
 748          * As workaround we drive the DAT3 line as GPIO and set it high.
 749          * This makes usdhc2 unusable in u-boot, but works for the
 750          * initialisation in Linux
 751          */
 752         imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
 753                                MUX_PAD_CTRL(NO_PAD_CTRL));
 754         gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
 755 #endif
 756         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 757 }
 758 #endif
 759
 760 struct display_info_t const displays[] = {
 761         {
 762                 .bus    = -1,
 763                 .addr   = 0,
 764                 .pixfmt = IPU_PIX_FMT_RGB24,
 765                 .detect = NULL,
 766                 .enable = enable_lvds,
 767                 .mode   = {
 768                         .name           = "lb07wv8",
 769                         .refresh        = 60,
 770                         .xres           = 800,
 771                         .yres           = 480,
 772                         .pixclock       = 30066,
 773                         .left_margin    = 88,
 774                         .right_margin   = 88,
 775                         .upper_margin   = 20,
 776                         .lower_margin   = 20,
 777                         .hsync_len      = 80,
 778                         .vsync_len      = 5,
 779                         .sync           = FB_SYNC_EXT,
 780                         .vmode          = FB_VMODE_NONINTERLACED
 781                 }
 782         }
 783 #if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3))
 784         , {
 785                 .bus    = -1,
 786                 .addr   = 0,
 787                 .pixfmt = IPU_PIX_FMT_RGB24,
 788                 .detect = NULL,
 789                 .enable = enable_spi_display,
 790                 .mode   = {
 791                         .name           = "lg4573",
 792                         .refresh        = 57,
 793                         .xres           = 480,
 794                         .yres           = 800,
 795                         .pixclock       = 37037,
 796                         .left_margin    = 59,
 797                         .right_margin   = 10,
 798                         .upper_margin   = 15,
 799                         .lower_margin   = 15,
 800                         .hsync_len      = 10,
 801                         .vsync_len      = 15,
 802                         .sync           = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
 803                                           FB_SYNC_VERT_HIGH_ACT,
 804                         .vmode          = FB_VMODE_NONINTERLACED
 805                 }
 806         }
 807 #endif
 808 };
 809 size_t display_count = ARRAY_SIZE(displays);
 810
 811 /* no console on this board */
 812 int board_cfb_skip(void)
 813 {
 814         return 1;
 815 }
 816
 817 iomux_v3_cfg_t nfc_pads[] = {
 818         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 819         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
 820         MX6_PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL),
 821         MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
 822         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
 823         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 824         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
 825         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
 826         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
 827         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
 828         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
 829         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
 830         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
 831         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
 832         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
 833         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
 834 };
 835
 836 static void setup_gpmi_nand(void)
 837 {
 838         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 839
 840         /* config gpmi nand iomux */
 841         imx_iomux_v3_setup_multiple_pads(nfc_pads,
 842                                          ARRAY_SIZE(nfc_pads));
 843
 844         /* gate ENFC_CLK_ROOT clock first,before clk source switch */
 845         clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 846
 847         /* config gpmi and bch clock to 100 MHz */
 848         clrsetbits_le32(&mxc_ccm->cs2cdr,
 849                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 850                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 851                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 852                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 853                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 854                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 855
 856         /* enable ENFC_CLK_ROOT clock */
 857         setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
 858
 859         /* enable gpmi and bch clock gating */
 860         setbits_le32(&mxc_ccm->CCGR4,
 861                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 862                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 863                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 864                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 865                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 866
 867         /* enable apbh clock gating */
 868         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 869 }
 870
 871 int board_init(void)
 872 {
 873         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 874
 875         /* address of boot parameters */
 876         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 877
 878         setup_spi();
 879
 880         setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 881                   &i2c_pad_info1);
 882         setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 883                   &i2c_pad_info2);
 884         setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 885                   &i2c_pad_info3);
 886         setup_i2c4();
 887
 888         /* SPI NOR Flash read only */
 889         gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
 890         gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
 891         gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
 892
 893         setup_board_gpio();
 894         setup_gpmi_nand();
 895         setup_board_spi();
 896
 897         /* GPIO_1 for USB_OTG_ID */
 898         clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
 899         imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
 900         return 0;
 901 }
 902
 903 int checkboard(void)
 904 {
 905         printf("Board: %s\n", CONFIG_BOARDNAME);
 906         return 0;
 907 }
 908
 909 #ifdef CONFIG_USB_EHCI_MX6
 910 int board_ehci_hcd_init(int port)
 911 {
 912         int ret;
 913
 914         ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr");
 915         if (!ret)
 916                 gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1);
 917         ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr");
 918         if (!ret)
 919                 gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1);
 920         return 0;
 921 }
 922
 923 int board_ehci_power(int port, int on)
 924 {
 925         if (port)
 926                 gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on);
 927         else
 928                 gpio_set_value(ARISTAINETOS_USB_H1_PWR, on);
 929
 930         return 0;
 931 }
 932 #endif
 933
 934 int board_fit_config_name_match(const char *name)
 935 {
 936         if (gd->board_type == BOARD_TYPE_4 &&
 937             strchr(name, 0x34))
 938                 return 0;
 939
 940         if (gd->board_type == BOARD_TYPE_7 &&
 941             strchr(name, 0x37))
 942                 return 0;
 943
 944         return -1;
 945 }
 946
 947 static void do_board_detect(void)
 948 {
 949         int ret;
 950         char s[30];
 951
 952         /* default use board type 7 */
 953         gd->board_type = BOARD_TYPE_7;
 954         if (env_init())
 955                 return;
 956
 957         ret = env_get_f("panel", s, sizeof(s));
 958         if (ret < 0)
 959                 return;
 960
 961         if (!strncmp("lg4573", s, 6))
 962                 gd->board_type = BOARD_TYPE_4;
 963 }
 964
 965 #ifdef CONFIG_DTB_RESELECT
 966 int embedded_dtb_select(void)
 967 {
 968         int rescan;
 969
 970         do_board_detect();
 971         fdtdec_resetup(&rescan);
 972
 973         return 0;
 974 }
 975 #endif