board/aristainetos/aristainetos-v2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2015
   4  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   5  *
   6  * Based on:
   7  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   8  *
   9  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  10  */
  11
  12 #include <init.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/imx-regs.h>
  15 #include <asm/arch/iomux.h>
  16 #include <asm/arch/mx6-pins.h>
  17 #include <env.h>
  18 #include <linux/errno.h>
  19 #include <asm/gpio.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/mxc_i2c.h>
  23 #include <asm/mach-imx/video.h>
  24 #include <mmc.h>
  25 #include <fsl_esdhc_imx.h>
  26 #include <miiphy.h>
  27 #include <netdev.h>
  28 #include <asm/arch/mxc_hdmi.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <linux/fb.h>
  31 #include <ipu_pixfmt.h>
  32 #include <asm/io.h>
  33 #include <asm/arch/sys_proto.h>
  34 #include <pwm.h>
  35 #include <micrel.h>
  36 #include <spi.h>
  37 #include <video.h>
  38 #include <../drivers/video/imx/ipu.h>
  39 #if defined(CONFIG_VIDEO_BMP_LOGO)
  40         #include <bmp_logo.h>
  41 #endif
  42
  43 #define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW |                    \
  44         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  45
  46 #if (CONFIG_SYS_BOARD_VERSION == 2)
  47         /* 4.3 display controller */
  48         #define ECSPI1_CS0              IMX_GPIO_NR(4, 9)
  49         #define ECSPI4_CS0              IMX_GPIO_NR(3, 29)
  50 #elif (CONFIG_SYS_BOARD_VERSION == 3)
  51         #define ECSPI1_CS0              IMX_GPIO_NR(2, 30)   /* NOR flash */
  52         /* 4.3 display controller */
  53         #define ECSPI1_CS1              IMX_GPIO_NR(4, 10)
  54 #endif
  55
  56 #define SOFT_RESET_GPIO         IMX_GPIO_NR(7, 13)
  57 #define SD2_DRIVER_ENABLE       IMX_GPIO_NR(7, 8)
  58
  59 struct i2c_pads_info i2c_pad_info3 = {
  60         .scl = {
  61                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  62                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  63                 .gp = IMX_GPIO_NR(1, 5)
  64         },
  65         .sda = {
  66                 .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
  67                 .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
  68                 .gp = IMX_GPIO_NR(1, 6)
  69         }
  70 };
  71
  72 struct i2c_pads_info i2c_pad_info4 = {
  73         .scl = {
  74                 .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
  75                 .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
  76                 .gp = IMX_GPIO_NR(1, 7)
  77         },
  78         .sda = {
  79                 .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
  80                 .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
  81                 .gp = IMX_GPIO_NR(1, 8)
  82         }
  83 };
  84
  85 iomux_v3_cfg_t const uart1_pads[] = {
  86         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  87         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  88         MX6_PAD_EIM_D19__UART1_CTS_B    | MUX_PAD_CTRL(UART_PAD_CTRL),
  89         MX6_PAD_EIM_D20__UART1_RTS_B    | MUX_PAD_CTRL(UART_PAD_CTRL),
  90 };
  91
  92 iomux_v3_cfg_t const uart2_pads[] = {
  93         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  94         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  95 };
  96
  97 iomux_v3_cfg_t const uart3_pads[] = {
  98         MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  99         MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 100         MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 101         MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 102 };
 103
 104 iomux_v3_cfg_t const uart4_pads[] = {
 105         MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 106         MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 107 };
 108
 109 iomux_v3_cfg_t const gpio_pads[] = {
 110         /* LED enable*/
 111         MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
 112         /* LED yellow */
 113         MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 114         /* LED red */
 115 #if (CONFIG_SYS_BOARD_VERSION == 2)
 116         MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
 117 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 118         MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 119 #endif
 120         /* LED green */
 121         MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
 122         /* LED blue */
 123         MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 124         /* spi flash WP protect */
 125         MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 126         /* spi CS 0 */
 127         MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 128         /* spi bus #2 SS driver enable */
 129         MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
 130         /* RST_LOC# PHY reset input (has pull-down!)*/
 131         MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
 132         /* SD 2 level shifter output enable */
 133         MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 134         /* SD1 card detect input */
 135         MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
 136         /* SD1 write protect input */
 137         MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
 138         /* SD2 card detect input */
 139         MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
 140         /* SD2 write protect input */
 141         MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 142         /* Touchscreen IRQ */
 143         MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
 144 };
 145
 146 static iomux_v3_cfg_t const misc_pads[] = {
 147         /* USB_OTG_ID = GPIO1_24*/
 148         MX6_PAD_ENET_RX_ER__USB_OTG_ID          | MUX_PAD_CTRL(NO_PAD_CTRL),
 149         /* H1 Power enable = GPIO1_0*/
 150         MX6_PAD_GPIO_0__USB_H1_PWR              | MUX_PAD_CTRL(NO_PAD_CTRL),
 151         /* OTG Power enable = GPIO4_15*/
 152         MX6_PAD_KEY_ROW4__USB_OTG_PWR           | MUX_PAD_CTRL(NO_PAD_CTRL),
 153 };
 154
 155 iomux_v3_cfg_t const enet_pads[] = {
 156         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
 157         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
 158         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 164         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
 165         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 166         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 167         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 168         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 169         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 170         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 171 };
 172
 173 static iomux_v3_cfg_t const backlight_pads[] = {
 174         /* backlight PWM brightness control */
 175         MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
 176         /* backlight enable */
 177         MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
 178         /* LCD power enable */
 179         MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
 180 };
 181
 182 static iomux_v3_cfg_t const ecspi1_pads[] = {
 183         MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 184         MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 185         MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 186 #if (CONFIG_SYS_BOARD_VERSION == 2)
 187         MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
 188 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 189         MX6_PAD_EIM_EB2__GPIO2_IO30  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 190         MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 191 #endif
 192 };
 193
 194 static void setup_iomux_enet(void)
 195 {
 196         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 197 }
 198
 199 #if (CONFIG_SYS_BOARD_VERSION == 2)
 200 iomux_v3_cfg_t const ecspi4_pads[] = {
 201         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
 202         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
 203         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
 204         MX6_PAD_EIM_A25__GPIO5_IO02  | MUX_PAD_CTRL(NO_PAD_CTRL),
 205         MX6_PAD_EIM_D29__GPIO3_IO29  | MUX_PAD_CTRL(NO_PAD_CTRL),
 206 };
 207 #endif
 208
 209 static iomux_v3_cfg_t const display_pads[] = {
 210         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
 211         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 212         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
 213         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
 214         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
 215         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
 216         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
 217         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
 218         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
 219         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
 220         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
 221         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
 222         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
 223         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
 224         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
 225         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
 226         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
 227         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
 228         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
 229         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
 230         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
 231         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
 232         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
 233         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
 234         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
 235         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
 236         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
 237         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
 238 };
 239
 240 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 241 {
 242         if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 243 #if (CONFIG_SYS_BOARD_VERSION == 2)
 244                 return IMX_GPIO_NR(5, 2);
 245
 246         if (bus == 0 && cs == 0)
 247                 return IMX_GPIO_NR(4, 9);
 248 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 249                 return ECSPI1_CS0;
 250
 251         if (bus == 0 && cs == 1)
 252                 return ECSPI1_CS1;
 253 #endif
 254         return -1;
 255 }
 256
 257 static void setup_spi(void)
 258 {
 259         int i;
 260
 261         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 262
 263 #if (CONFIG_SYS_BOARD_VERSION == 2)
 264         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
 265 #endif
 266
 267         for (i = 0; i < 4; i++)
 268                 enable_spi_clk(true, i);
 269
 270         gpio_direction_output(ECSPI1_CS0, 1);
 271 #if (CONFIG_SYS_BOARD_VERSION == 2)
 272         gpio_direction_output(ECSPI4_CS1, 0);
 273         /* set cs0 to high (second device on spi bus #4) */
 274         gpio_direction_output(ECSPI4_CS0, 1);
 275 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 276         gpio_direction_output(ECSPI1_CS1, 1);
 277 #endif
 278 }
 279
 280 static void setup_iomux_uart(void)
 281 {
 282         switch (CONFIG_MXC_UART_BASE) {
 283         case UART1_BASE:
 284                 imx_iomux_v3_setup_multiple_pads(uart1_pads,
 285                                                  ARRAY_SIZE(uart1_pads));
 286                 break;
 287         case UART2_BASE:
 288                 imx_iomux_v3_setup_multiple_pads(uart2_pads,
 289                                                  ARRAY_SIZE(uart2_pads));
 290                 break;
 291         case UART3_BASE:
 292                 imx_iomux_v3_setup_multiple_pads(uart3_pads,
 293                                                  ARRAY_SIZE(uart3_pads));
 294                 break;
 295         case UART4_BASE:
 296                 imx_iomux_v3_setup_multiple_pads(uart4_pads,
 297                                                  ARRAY_SIZE(uart4_pads));
 298                 break;
 299         }
 300 }
 301
 302 int board_phy_config(struct phy_device *phydev)
 303 {
 304         /* control data pad skew - devaddr = 0x02, register = 0x04 */
 305         ksz9031_phy_extended_write(phydev, 0x02,
 306                                    MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
 307                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 308         /* rx data pad skew - devaddr = 0x02, register = 0x05 */
 309         ksz9031_phy_extended_write(phydev, 0x02,
 310                                    MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
 311                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 312         /* tx data pad skew - devaddr = 0x02, register = 0x06 */
 313         ksz9031_phy_extended_write(phydev, 0x02,
 314                                    MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
 315                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
 316         /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
 317         ksz9031_phy_extended_write(phydev, 0x02,
 318                                    MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
 319                                    MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
 320
 321         if (phydev->drv->config)
 322                 phydev->drv->config(phydev);
 323
 324         return 0;
 325 }
 326
 327 int board_eth_init(bd_t *bis)
 328 {
 329         setup_iomux_enet();
 330         return cpu_eth_init(bis);
 331 }
 332
 333 static int rotate_logo_one(unsigned char *out, unsigned char *in)
 334 {
 335         int   i, j;
 336
 337         for (i = 0; i < BMP_LOGO_WIDTH; i++)
 338                 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 339                         out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
 340                         in[i * BMP_LOGO_WIDTH + j];
 341         return 0;
 342 }
 343
 344 /*
 345  * Rotate the BMP_LOGO (only)
 346  * Will only work, if the logo is square, as
 347  * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
 348  */
 349 void rotate_logo(int rotations)
 350 {
 351         unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
 352         unsigned char *in_logo;
 353         int   i, j;
 354
 355         if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
 356                 return;
 357
 358         in_logo = bmp_logo_bitmap;
 359
 360         /* one 90 degree rotation */
 361         if (rotations == 1  ||  rotations == 2  ||  rotations == 3)
 362                 rotate_logo_one(out_logo, in_logo);
 363
 364         /* second 90 degree rotation */
 365         if (rotations == 2  ||  rotations == 3)
 366                 rotate_logo_one(in_logo, out_logo);
 367
 368         /* third 90 degree rotation */
 369         if (rotations == 3)
 370                 rotate_logo_one(out_logo, in_logo);
 371
 372         /* copy result back to original array */
 373         if (rotations == 1  ||  rotations == 3)
 374                 for (i = 0; i < BMP_LOGO_WIDTH; i++)
 375                         for (j = 0; j < BMP_LOGO_HEIGHT; j++)
 376                                 in_logo[i * BMP_LOGO_WIDTH + j] =
 377                                 out_logo[i * BMP_LOGO_WIDTH + j];
 378 }
 379
 380 static void enable_display_power(void)
 381 {
 382         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 383                                          ARRAY_SIZE(backlight_pads));
 384
 385         /* backlight enable */
 386         gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
 387         /* LCD power enable */
 388         gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
 389
 390         /* enable backlight PWM 1 */
 391         if (pwm_init(0, 0, 0))
 392                 goto error;
 393         /* duty cycle 500ns, period: 3000ns */
 394         if (pwm_config(0, 50000, 300000))
 395                 goto error;
 396         if (pwm_enable(0))
 397                 goto error;
 398         return;
 399
 400 error:
 401         puts("error init pwm for backlight\n");
 402         return;
 403 }
 404
 405 static void enable_lvds(struct display_info_t const *dev)
 406 {
 407         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 408         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 409         int reg;
 410         s32 timeout = 100000;
 411
 412         /* set PLL5 clock */
 413         reg = readl(&ccm->analog_pll_video);
 414         reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
 415         writel(reg, &ccm->analog_pll_video);
 416
 417         /* set PLL5 to 232720000Hz */
 418         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 419         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
 420         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 421         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 422         writel(reg, &ccm->analog_pll_video);
 423
 424         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
 425                &ccm->analog_pll_video_num);
 426         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
 427                &ccm->analog_pll_video_denom);
 428
 429         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 430         writel(reg, &ccm->analog_pll_video);
 431
 432         while (timeout--)
 433                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 434                         break;
 435         if (timeout < 0)
 436                 printf("Warning: video pll lock timeout!\n");
 437
 438         reg = readl(&ccm->analog_pll_video);
 439         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 440         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 441         writel(reg, &ccm->analog_pll_video);
 442
 443         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 444         reg = readl(&ccm->cs2cdr);
 445         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 446                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 447         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 448                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 449         writel(reg, &ccm->cs2cdr);
 450
 451         reg = readl(&ccm->cscmr2);
 452         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 453         writel(reg, &ccm->cscmr2);
 454
 455         reg = readl(&ccm->chsccdr);
 456         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 457                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 458         writel(reg, &ccm->chsccdr);
 459
 460         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 461               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 462               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 463               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 464               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 465               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 466               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 467         writel(reg, &iomux->gpr[2]);
 468
 469         reg = readl(&iomux->gpr[3]);
 470         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 471                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 472                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 473         writel(reg, &iomux->gpr[3]);
 474
 475         return;
 476 }
 477
 478 static void enable_spi_display(struct display_info_t const *dev)
 479 {
 480         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 481         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 482         int reg;
 483         s32 timeout = 100000;
 484
 485 #if defined(CONFIG_VIDEO_BMP_LOGO)
 486         rotate_logo(3);  /* portrait display in landscape mode */
 487 #endif
 488
 489         /*
 490          * set ldb clock to 28341000 Hz calculated through the formula:
 491          * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
 492          * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
 493          * see:
 494          * https://community.freescale.com/thread/308170
 495          */
 496         ipu_set_ldb_clock(28341000);
 497
 498         reg = readl(&ccm->cs2cdr);
 499
 500         /* select pll 5 clock */
 501         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 502                 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 503         writel(reg, &ccm->cs2cdr);
 504
 505         /* set PLL5 to 197994996Hz */
 506         reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
 507         reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
 508         reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
 509         reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
 510         writel(reg, &ccm->analog_pll_video);
 511
 512         writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
 513                &ccm->analog_pll_video_num);
 514         writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
 515                &ccm->analog_pll_video_denom);
 516
 517         reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
 518         writel(reg, &ccm->analog_pll_video);
 519
 520         while (timeout--)
 521                 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
 522                         break;
 523         if (timeout < 0)
 524                 printf("Warning: video pll lock timeout!\n");
 525
 526         reg = readl(&ccm->analog_pll_video);
 527         reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
 528         reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
 529         writel(reg, &ccm->analog_pll_video);
 530
 531         /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
 532         reg = readl(&ccm->cs2cdr);
 533         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 534                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 535         reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 536                 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 537         writel(reg, &ccm->cs2cdr);
 538
 539         reg = readl(&ccm->cscmr2);
 540         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 541         writel(reg, &ccm->cscmr2);
 542
 543         reg = readl(&ccm->chsccdr);
 544         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 545                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 546         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
 547         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
 548         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
 549         reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 550         writel(reg, &ccm->chsccdr);
 551
 552         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 553               | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 554               | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
 555               | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 556               | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
 557               | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 558               | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 559         writel(reg, &iomux->gpr[2]);
 560
 561         reg = readl(&iomux->gpr[3]);
 562         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 563                | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 564                   << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 565         writel(reg, &iomux->gpr[3]);
 566
 567         imx_iomux_v3_setup_multiple_pads(
 568                 display_pads,
 569                  ARRAY_SIZE(display_pads));
 570
 571         return;
 572 }
 573 static void setup_display(void)
 574 {
 575         enable_ipu_clock();
 576         enable_display_power();
 577 }
 578
 579 static void setup_iomux_gpio(void)
 580 {
 581         imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
 582 }
 583
 584 static void set_gpr_register(void)
 585 {
 586         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 587
 588         writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
 589                IOMUXC_GPR1_EXC_MON_SLVE |
 590                (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
 591                IOMUXC_GPR1_ACT_CS0,
 592                &iomuxc_regs->gpr[1]);
 593         writel(0x0, &iomuxc_regs->gpr[8]);
 594         writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
 595                IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
 596                &iomuxc_regs->gpr[12]);
 597 }
 598
 599 int board_early_init_f(void)
 600 {
 601         setup_iomux_uart();
 602         setup_iomux_gpio();
 603
 604         gpio_direction_output(SOFT_RESET_GPIO, 1);
 605         gpio_direction_output(SD2_DRIVER_ENABLE, 1);
 606         setup_display();
 607         set_gpr_register();
 608         return 0;
 609 }
 610
 611 static void setup_i2c4(void)
 612 {
 613         setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
 614                   &i2c_pad_info4);
 615 }
 616
 617 static void setup_board_gpio(void)
 618 {
 619         /* enable all LEDs */
 620         gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */
 621         gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
 622
 623         /* switch off Status LEDs */
 624 #if (CONFIG_SYS_BOARD_VERSION == 2)
 625         gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
 626         gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
 627         gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
 628         gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
 629         gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
 630         gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
 631         gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
 632         gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
 633 #elif (CONFIG_SYS_BOARD_VERSION == 3)
 634         gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
 635         gpio_direction_output(IMX_GPIO_NR(6, 16), 0);
 636         gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */
 637         gpio_direction_output(IMX_GPIO_NR(5, 0), 0);
 638         gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
 639         gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
 640         gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
 641         gpio_direction_output(IMX_GPIO_NR(2, 29), 0);
 642 #endif
 643 }
 644
 645 static void setup_board_spi(void)
 646 {
 647         /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */
 648         gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
 649 }
 650
 651 int board_late_init(void)
 652 {
 653         char *my_bootdelay;
 654         char bootmode = 0;
 655         char const *panel = env_get("panel");
 656
 657         /*
 658          * Check the boot-source. If booting from NOR Flash,
 659          * disable bootdelay
 660          */
 661         gpio_request(IMX_GPIO_NR(7, 6), "bootsel0");
 662         gpio_direction_input(IMX_GPIO_NR(7, 6));
 663         gpio_request(IMX_GPIO_NR(7, 7), "bootsel1");
 664         gpio_direction_input(IMX_GPIO_NR(7, 7));
 665         gpio_request(IMX_GPIO_NR(7, 1), "bootsel2");
 666         gpio_direction_input(IMX_GPIO_NR(7, 1));
 667         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0;
 668         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1;
 669         bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2;
 670
 671         if (bootmode == 7) {
 672                 my_bootdelay = env_get("nor_bootdelay");
 673                 if (my_bootdelay != NULL)
 674                         env_set("bootdelay", my_bootdelay);
 675                 else
 676                         env_set("bootdelay", "-2");
 677         }
 678
 679         /* if we have the lg panel, we can initialze it now */
 680         if (panel)
 681                 if (!strcmp(panel, displays[1].mode.name))
 682                         lg4573_spi_startup(CONFIG_LG4573_BUS,
 683                                            CONFIG_LG4573_CS,
 684                                            10000000, SPI_MODE_0);
 685
 686         return 0;
 687 }